Transmitter and repetition method thereof

ABSTRACT

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

CROSS-REFERENCE TO THE RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 16/503,945, filed Jul. 5, 2019, which is a continuation of U.S. application Ser. No. 15/343,933, filed Nov. 4, 2016, now U.S. Pat. No. 10,389,390 issued Aug. 20, 2019, which is a continuation of U.S. application Ser. No. 15/099,998, filed Apr. 15, 2016, now U.S. Pat. No. 9,525,437 issued Dec. 20, 2016, which is a continuation of U.S. patent application Ser. No. 15/052,049, filed Feb. 24, 2016, now U.S. Pat. No. 10,027,350 issued Jul. 17, 2018, which claims priority from Korean Patent Application No. 10-2015-0137187, filed on Sep. 27, 2015 and U.S. Provisional Application Nos. 62/120,108 and 62/126,902, filed on Feb. 24, 2015 and Mar. 2, 2015, respectively. The entire disclosures of the prior applications are considered part of the disclosure of this continuation application, and are hereby incorporated by reference.

BACKGROUND 1. Field

Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a bit repetition method thereof, and more particularly, to a transmitter processing and transmitting input bits and a bit repetition method thereof.

2. Description of the Related Art

Broadcast communication services in information oriented society of the 21^(st) century are entering an era of digitalization, multi-channelization, bandwidth broadening, and high quality. In particular, as a high definition digital television (TV), a personal media player (PMP), and portable broadcasting devices are widespread, digital broadcasting services have an increased demand for supporting improved transmitting and receiving schemes.

According to such demand, standard groups set up various standards to provide signal transmission and reception services satisfying the needs of a user. Still, however, a method of providing services to a user with more improved performance is required.

SUMMARY

Exemplary embodiments of the inventive concept may overcome disadvantages of related art signal transmitter and receiver and methods thereof. However, these embodiments are not required to or may not overcome such disadvantages.

The exemplary embodiments provide a transmitter, a receiver and a repetition method of repeating bits of a broadcasting signal which enables transmission of the repeated bits.

According to an aspect of an exemplary embodiment, there is provided a transmitter which may include: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

The input bits may include zero bits padded in the input bits, and the repeater is configured to calculate a number of bits to be selected and added after the input bits based on a number of bits other than the padded zero bits in the input bits.

The input bits may include outer encoded bits, and the repeater is configured to calculate a number of bits to be selected and added after the input bits based on a number of the outer encoded bits.

The repeater may calculate the number of the bits to be selected and added after the input bits, based on Equation 8.

The puncturer may puncture the part of the parity bits from a last bit of the parity bits.

When the calculated number of the bits to be selected and added after the input bits is equal to or less than the number of the parity bits, the repeater may select bits as many as the calculated number from a first bit of the parity bits and add the selected bits after the input bits.

When the calculated number of the bits to be selected and added after the input bits is greater than the number of the parity bits, the repeater may select all the parity bits and add the selected parity bits after the input bits, and additionally select bits as many as a number obtained by subtracting the number of the parity bits from the calculated number of the added bits from a first bit of the parity bits and add the additionally selected bits after the added parity bits.

According to an aspect of another exemplary embodiment, there is provided a repetition method of a transmitter which nay include: encoding input bits to generate an LDPC codeword including the input bits and parity bits; selecting at least a part of bits constituting the LDPC codeword and adding the selected bits after the input bits; and puncturing at least a part of the parity bits.

The input bits may include zero bits padded in the input bits, and the method may further include calculating the number of bits to be selected and added after the input bits, before the adding, based on a number of bits other than the padded zero bits in the input bits.

The input bits may include outer encoded bits, and the method may further include calculating the number of bits to be selected and added after the input bits, before the adding, based on a number of outer encoded bits.

The above calculating may be performed based on Equation 8.

The puncturing may be performed from a last bit of the parity bits.

When the calculated number of the bits to be selected and added after the input bits is equal to or less than the number of the parity bits, the selecting and adding may include selecting bits as many as the calculated number from a first bit of the parity bits and adding the selected bits after the input bits.

When the calculated number of the bits to be selected and added after the input bits is greater than the number of the parity bits, the selecting and adding may include: selecting all the parity bits and adding the selected parity bits after the input bits; and additionally selecting bits as many as a number obtained by subtracting the number of the parity bits from the calculated number of the added bits from a first bit of the parity bits and adding the additionally selected bits after the added parity bits.

As described above, according to the exemplary embodiments, some of the parity bits may be additionally transmitted to improve decoding performance at the receiver of the input bits and the parity bits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for describing a configuration of a transmitter according to an exemplary embodiment;

FIGS. 2 and 3 are diagrams for describing parity check matrices according to exemplary embodiments;

FIGS. 4 to 7 are block diagrams for describing repetition according to exemplary embodiments;

FIGS. 8 to 11 are block diagrams for describing puncturing according to exemplary embodiments;

FIG. 12 is a diagram for describing a frame structure according to an exemplary embodiment;

FIGS. 13 and 14 are block diagrams for describing detailed configurations of a transmitter according to exemplary embodiments;

FIGS. 15 to 28 are diagrams for describing methods for processing signaling according to exemplary embodiments;

FIGS. 29 to 31 are diagrams for describing repetition methods according to exemplary embodiments;

FIGS. 32 and 33 are block diagrams for describing configurations of a receiver according to exemplary embodiments;

FIGS. 34 and 35 are diagrams for describing examples of combining LLR values of a receiver according to exemplary embodiments;

FIG. 36 is a diagram illustrating an example of providing information on a length of an L1 signaling according to an exemplary embodiment; and

FIG. 37 is a flow chart for describing a repetition method according to an exemplary embodiment.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENT

Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to accompanying drawings.

FIG. 1 is a block diagram for describing a configuration of a transmitter according to an exemplary embodiment.

Referring to FIG. 1, a transmitter 100 includes a Low Density Parity Check (LDPC) encoder 110, a repeater 120 and a puncturer 130.

The LDPC encoder 110 may encode input bits. In other words, the LDPC encoder 110 may perform LDPC encoding on the input bits to generate parity bits, that is, LDPC parity bits.

Here, the input bits are LDPC information bits for the LDPC encoding and may include outer-encoded bits and zero bits (that is, bits having a 0 value), in which the outer-encoded bits include information bits and parity bits (or parity check bits) generated by outer-encoding the information bits.

Hereinafter, the information bits may be signaling (alternatively referred to as “signaling bits” or “signaling information”). The signaling may include information required for a receiver 200 (as illustrated in FIG. 32 or 33) to process service data (for example, broadcasting data) transmitted from the transmitter 100.

Further, outer encoding is a coding operation which is performed before inner encoding in a concatenated coding operation, and may use various encoding schemes such as Bose, Chaudhuri, Hocquenghem (BCH) encoding and/or cyclic redundancy check (CRC) encoding. In this case, the inner encoding may be the LDPC encoding.

For LDPC encoding, a predetermined number of LDPC information bits depending on a code rate and a code length are required. Therefore, when the number of outer-encoded bits generated by outer-encoding the information bits is less than the required number of LDPC information bits, an appropriate number of zero bits are padded to obtain the required number of LDPC information bits for the LDPC encoding. Therefore, the outer-encoded bits and the padded zero bits may configure the LDPC information bits as many as the number of bits required for the LDPC encoding.

Since the padded zero bits are bits required to obtain the predetermined number of bits for the LDPC encoding, the padded zero bits are LDPC-encoded and then are not transmitted to the receiver 200. As such, a procedure of padding zero bits, and then, not transmitting the padded zero bits to the receiver 200 may be called shortening. In this case, the padded zero bits may be called shortening bits (or shortened bits).

For example, it is assumed that the number of information bits is K_(sig) and the number of bits when M_(outer) parity bits are added to the information bits by the outer encoding, that is, the number of outer-encoded bits including the information bits and the parity bits is N_(outer) (=K_(sig)+M_(outer)).

In this case, when the number N_(outer) of outer-encoded bits is less than the number K_(ldpc) of LDPC information bits, K_(ldpc)−N_(outer) number of zero bits are padded so that the outer-encoded bits and the padded zero bits may configure the LDPC information bits together.

Meanwhile, the foregoing example describes that zero bits are padded, which is only one example.

When the information bits are signaling for data or a service data, a length of the information bits may vary depending on the amount of the data. Therefore, when the number of information bits is greater than the number of LDPC information bits required for the LDPC encoding, the information bits may be segmented below a predetermined value.

Therefore, when the number of information bits or the number of segmented information bits is less than the number obtained by subtracting the number of parity bits (that is, M_(outer)) generated by the outer encoding from the number of LDPC information bits, zero bits are padded as many as the number obtained by subtracting the number of outer-encoded bits from the number of LDPC information bits so that the LDPC information bits may be formed of the outer-encoded bits and the padded zero bits.

However, when the number of information bits or the number of segmented information bits are equal to the number obtained by subtracting the number of parity bits generated by the outer encoding from the number of LDPC information bits, the LDPC information bits may be formed of the outer-encoded bits without the padded zero bits.

Further, the foregoing example describes that the information bits are outer-encoded, which is only one example. However, the information bits may not be outer-encoded and configure the LDPC information bits along with the zero bits padded depending on the number of information bits or only the information bits may configure the LDPC information bits without separately padding.

Meanwhile, for convenience of explanation, the outer encoding will be described below under the assumption that it is performed by the BCH encoding.

In detail, the input bits will be described under the assumption that they include BCH-encoded bits and zero bits, the BCH-encoded bits including the information bits and BCH parity-check bits (or BCH parity bits) generated by BCH-encoding the information bits.

That is, it is assumed that the number of information bits is K_(sig) and the number of bits when M_(outer) BCH parity check bits by the BCH encoding are added to the information bits, that is, the number of BCH encoded bits including the information bits and the BCH parity check bits is N_(outer)(=K_(sig)+M_(outer)). Here, M_(outer)=168.

Further, the foregoing example describes that zero bits, which will be shortened, are padded, which is only one example. That is, since zero bits are bits having a value preset by the transmitter 100 and the receiver 200 and padded only to form LDPC information bits along with information bits including information to be substantially transmitted to the receiver 200, bits having another value (for example, 1) preset by the transmitter 100 and the receiver 200 instead of zero bits may be padded for the shortening.

The LDPC encoder 110 may systematically encode the LDPC information bits to generate LDPC parity bits, and output an LDPC codeword (or LDPC-encoded bits) formed of the LDPC information bits and the LDPC parity bits. That is, an LDPC code is a systematic code, and therefore, the LDPC codeword may be formed of the LDPC information bits before being LDPC-encoded and the LDPC parity bits generated by the LDPC encoding.

For example, the LDPC encoder 110 may LDPC-encode K_(ldpc) LDPC information bits i=(i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹) to generate N_(ldpc_parity) LDPC parity bits (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹) and output an LDPC codeword Λ=(c₀, c₁, . . . , c_(N) _(inner) ⁻¹)=(i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(inner) _(−K) _(ldpc) ⁻¹) formed of N_(inner) (=K_(ldpc)+N_(ldpc_parity)) bits.

In this case, the LDPC encoder 110 may perform LDPC encoding on the input bits (i.e., LDPC information bits) at various code rates to generate an LDPC codeword having a predetermined length.

For example, the LDPC encoder 110 may perform the LDPC encoding on 3240 input bits at a code rate of 3/15 to generate an LDPC codeword formed of 16200 bits. As another example, the LDPC encoder 110 may perform the LDPC encoding on 6480 input bits at a code rate of 6/15 to generate the LDPC codeword formed of 16200 bits.

Meanwhile, a process of performing the LDPC encoding is a process of generating an LDPC codeword to satisfy H·C^(T)=0, and thus, the LDPC encoder 110 may use a parity check matrix to perform the LDPC encoding. Here, H represents the parity check matrix and C represents the LDPC codeword.

Hereinafter, a structure of the parity check matrix according to various exemplary embodiments will be described with reference to the accompanying drawings. In the parity check matrix, elements of a portion other than 1 are 0.

For example, the parity check matrix according to the exemplary embodiment may have a structure as illustrated in FIG. 2.

Referring to FIG. 2, a parity check matrix 20 may be formed of five sub-matrices A, B, C, Z and D. Hereinafter, for describing the structure of the parity check matrix 20, each matrix structure will be described.

The sub-matrix A is formed of K columns and g rows, and the sub-matrix C is formed of K+g columns and N−K−g rows. Here, K (or K_(ldpc)) represents a length of LDPC information bits and N (or N_(inner)) represents a length of the LDPC codeword.

Further, in the sub-matrices A and C, indexes of a row in which 1 is positioned in a 0-th column of an i-th column group may be defined based on Table 1 when the length of the LDPC codeword is 16200 and the code rate is 3/15. Meanwhile, the number of columns belonging to the same column group may be 360.

TABLE 1   8 372 841 4522 5253 7430 8542 9622 10550 11896 11968 80 255 557 1511 3549 9239 5422 5497 7157 7854 11

67 257 406 792 2916 3072 3214 363

 4090 8175 8892 9603 80 150 346 1883 6838 7

18 9482 10366 10514 11468 12341 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990 1

2 283 696 3364 4514 4649 7260 7370 11925 11986 12092 127 1034 1044 1842 3184 3397 5931 7577 11698 32339 12689 107 513 979 3934 4374 4658 7286 7808 8830 10804 10893 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876 2932 6241 7136 7825 8541 9403 9837 11679 12377 12810 2211 2288 3937 4310 5952 6397 9692 10445 11064 11272

indicates data missing or illegible when filed

Hereinafter, positions (alternatively referred to as “indexes” or “index values”) of a row in which 1 is positioned in the sub-matrices A and C will be described in detail with reference to, for example, Table 1.

When the length of the LDPC codeword is 16200 and the code rate is 3/15, coding parameters M₁, M₂, Q₁ and Q₂ based on the parity check matrix 200 each are 1080, 11880, 3 and 33.

Here, Q₁ represents a size at which columns belonging to the same column group in the sub-matrix A are cyclic-shifted and Q₂ represents a size at which columns belonging to the same column group in the sub-matrix C are cyclic-shifted.

Further, Q₁=M₁/L, Q₂=M₂/L, M₁=g, M₂=N−K−g and L represents an interval at which patterns of the column are repeated in the sub-matrices A and C, respectively, that is, the number (for example, 360) of columns belonging to the same column group.

The indexes of the row in which 1 is positioned in the sub-matrices A and C, respectively, may be determined based on an M₁ value.

For example, in above Table 1, since M₁=1080, the position of the row in which 1 is positioned in the 0-th column of the i-th column group in the matrix A may be determined based on values less than 1080 among index values of above Table 1, and the position of the row in which 1 is positioned in the 0-th column of the i-th column group in the sub-matrix C may be determined based on values equal to or greater than 1080 among the index values of above Table 1.

In detail, a sequence corresponding to the 0-th column group in above Table 1 is “8 372 841 4522 5253 7430 8542 9822 10550 11896 11988”. Therefore, in the 0-th column of the 0-th column group in the sub-matrix A, 1 may be positioned in an eighth row, a 372-th row, and an 841-th row, respectively, and in the 0-th column of the 0-th column group in the sub-matrix C, 1 may be positioned in a 4522-th row, a 5253-th row, a 7430-th row, an 8542-th row, a 9822-th row, a 10550-th row, a 11896-th row, and a 11988-row, respectively.

In the matrix A, when the position of 1 is defined in the 0-th columns of each column group, it may be cyclic-shifted by the Q₁ to define a position of a row in which 1 is positioned in other columns of each column group, and in the sub-matrix C, when the position of 1 is defined in the 0-th columns of each column group, it may be cyclic-shifted by the Q₂ to define a position of a row in which 1 is positioned in other columns of each column group.

In the foregoing example, in the 0-th column of the 0-th column group in the sub-matrix A, 1 is positioned in an eighth row, a 372-th row, and an 841-th row. In this case, since Q₁=3, indexes of a row in which 1 is positioned in a first column of the 0-th column group may be 11(=8+3), 375(=372+3), and 844(=841+3) and indexes of a row in which 1 is positioned in a second column of the 0-th column group may be 14(=11+3), 378(=375+3), and 847(=844+3).

In the 0-th column of the 0-th column group in the sub-matrix C, 1 is positioned in a 4522-th row, a 5253-th row, a 7430-th row, a 8542-th row, a 9822-th row, a 10550-th row, a 11896-th row, and a 11988-th row. In this case, since Q₂=33, the indexes of the row in which 1 is positioned in the first column of the 0-th column group may be 4555(=4522+33), 5286(=5253+33), 7463(=7430+33), 8575(=8542+33), 9855(=9822+33) 10583(=10550+33), 11929(=11896+33), and 12021(=11988+33) and the indexes of the row in which 1 is positioned in the second column of the 0-th column group may be 4588(=4555+33), 5319(=5286+33), 7496(=7463+33), 8608(=8575+33), 9888(=9855+33), 10616(=10583+33), 11962(=11929+33), and 12054(=12021+33).

According to the scheme, the positions of the row in which 1 is positioned in all column groups in the sub-matrices A and C may be defined.

Meanwhile, the matrix B is a dual diagonal matrix, the sub-matrix D is an identity matrix, and the sub-matrix Z is a zero matrix.

As a result, the structure of the parity check matrix 20 as illustrated in FIG. 2 may be defined by the sub-matrices A, B, C, D and Z having the above structure.

Hereinafter, a method for performing, by the LDPC encoder 110, the LDPC encoding based on the parity check matrix 20 as illustrated in FIG. 2 will be described.

The LDPC code may be used to encode an information block S=(s₀, s₁, . . . , s_(K−1)). In this case, to generate an LDPC codeword Λ=(λ₀, λ₁, . . . , λ_(N-1)) having a length of N=K+M₁+M₂, parity blocks P=(p₀, p₁, . . . , p_(M) ₁ _(+M) ₂ ⁻¹) from the information block S may be systematically encoded.

As a result, the LDPC codeword may be Λ=(s₀, s₁, . . . , s_(K−1), p₀, p₁, . . . , p_(M) ₁ _(+M) ₂ ⁻¹).

Here, M₁ and M₂ each represent a size of parity sub-matrices corresponding to the dual diagonal sub-matrix B and the identity sub-matrix D, respectively, in which M₁=g and M₂=N−K−g.

A process of calculating parity bits may be represented as follows. Hereinafter, for convenience of explanation, a case in which the parity check matrix 20 is defined as above Table 1 will be described as one example.

Step 1) It is initialized to λ_(i)=s_(i)(i=0, 1, . . . , K−1), p_(j)=0 (j=0, 1, . . . , M₁+M₂−1).

Step 2) A first information bit λ₀ is accumulated in a parity bit address defined in the first row of above Table 1.

Step 3) For the next L−1 information bits λ_(m)(m=1, 2, . . . , L−1), λ_(m) is accumulated in the parity bit address calculated based on following Equation 1.

(x+m×Q ₁)mod M ₁(if x<M ₁)

M ₁+{(x−M ₁ +m×Q ₂)mod M ₂} (if x≥M ₁)  (1),

In above Equation 1, x represents an address of a parity bit accumulator corresponding to a first information bit λ₀. Further, Q₁=M₁/L and Q₂=M₂/L.

Further, Q₁=M₁/L and Q₂=M₂/L. In this case, since the length of the LDPC codeword is 16200 and the code rate is 3/15, M₁=1080, M₂=11880, Q₁=3, Q₂=33, L=360.

Step 4) Since the parity bit address like the second row of above Table 1 is given to an L-th information bit λ_(L), similar to the foregoing scheme, the parity bit address for next L−1 information bits λ_(m) (m=L+1, L+2, . . . , 2L−1) is calculated by the scheme described in the above step 3). In this case, x represents the address of the parity bit accumulator corresponding to the information bit L and may be obtained based on the second row of above Table 1.

Step 5) For L new information bits of each group, the new rows of above Table 1 are set as the address of the parity bit accumulator and thus the foregoing process is repeated.

Step 6) After the foregoing process is repeated from the codeword bit λ₀ to λ_(K−1), a value for following Equation 2 is sequentially calculated from i=1.

P _(i) =P _(i) ⊕P _(i-1)(i=1,2, . . . ,M ₁−1)  (2)

Step 7) The parity bits λ_(K) to λ_(K+M) ₁ ⁻¹ corresponding to the dual diagonal sub-matrix B are calculated based on following Equation 3.

λ_(K+L×t+s) =p _(Q) ₁ _(×s+t)(0≤s<L,0≤t<Q ₁)  (3)

Step 8) The address of the parity bit accumulator for the L new codeword bits λ_(K) to λ_(K+M) ₁ ⁻¹ of each group is calculated based on the new row of above Table 1 and above Equation 1.

Step 9) After the codeword bits λ_(K) to λ_(K+M) ₁ ⁻¹ are applied, the parity bits λ_(K+M) ₁ to λ_(K+M) ₁ _(+M) ₂ ⁻¹ corresponding to the sub-matrix D are calculated based on following Equation 4.

λ_(K+M) ₁ _(+L×t+s) =p _(M) ₁ _(+Q) ₂ _(×s+t)(0≤s<L,0≤t<Q ₂)  (4)

As a result, the parity bits may be calculated by the above scheme. However, this is only one example, and thus, the scheme for calculating the parity bits based on the parity check matrix as illustrated in FIG. 2 may be variously defined.

As such, the LDPC encoder 110 may perform the LDPC encoding based on above Table 1 to generate the LDPC codeword.

In detail, the LDPC encoder 110 may perform the LDPC encoding on 3240 input bits, that is, the LDPC information bits at the code rate of 3/15 based on above Table 1 to generate 12960 LDPC parity bits, and output the LDPC parity bits and the LDPC codeword including the LDPC parity bits. In this case, the LDPC codeword may be formed of 16200 bits.

As another example, the parity check matrix according to the exemplary embodiment may have a structure as illustrated in FIG. 3.

Referring to FIG. 3, a parity check matrix 30 is formed of an information sub-matrix 31 which is a sub-matrix corresponding to the information bits (that is, LDPC information bits) and a parity sub-matrix 32 which is a sub-matrix corresponding to the parity bits (that is, LDPC parity bits).

The information sub-matrix 31 includes K_(ldpc) columns and the parity sub-matrix 32 includes N_(ldpc_parity)=N_(inner)−K_(ldpc) columns. Meanwhile, the number of rows of the parity check matrix 30 is equal to the number N_(ldpc_parity)=N_(inner)−K_(ldpc) of columns of the parity sub-matrix 32.

Further, in the parity check matrix 30, N_(inner) represents the length of the LDPC codeword, K_(ldpc) represents the length of the information bits, and N_(ldpc_parity)=N_(inner)−K_(ldpc) represents the length of the parity bits.

Hereinafter, the structures of the information sub-matrix 31 and the parity sub-matrix 32 will be described.

The information sub-matrix 31 is a matrix including the K_(ldpc) columns (that is, 0-th column to (K_(ldpc)−1)-th column) and depends on the following rule.

First, the K_(ldpc) columns configuring the information sub-matrix 31 belong to the same group by M numbers and are divided into a total of K_(ldpc)/M column groups. The columns belonging to the same column group have a relationship that they are cyclic-shifted by Q_(ldpc) from one another. That is, the Q_(ldpc) may be considered as a cyclic shift parameter value for columns of the column group in the information sub-matrix configuring the parity check matrix 30.

Here, the M is an interval (for example, M=360) at which the patterns of the columns in the information sub-matrix 31 are repeated and Q_(ldpc) is a size at which each column in the information sub-matrix 31 is cyclic-shifted. The M is a common divisor of the N_(inner) and the K_(ldpc) and is determined so that Q_(ldpc)=(N_(inner)−K_(ldpc))/M is established. Here, M and Q_(ldpc) are integers, respectively, and K_(ldpc)/M also becomes an integer. Meanwhile, the M and the Q_(ldpc) may have various values depending on the length of the LDPC codeword and the code rate.

For example, when the M=360, the length N_(inner) of the LDPC codeword is 16200, and the code rate is 6/15, the Q_(ldpc) may be 27.

Second, if a degree (herein, the degree is the number of values is positioned in the column and the degrees of all the columns belonging to the same column group are the same) of a 0-th column of an i-th (i=0, 1, . . . , K_(ldpc)/M−1) column group is set to be D_(i) and positions (or index) of each row in which 1 is positioned in the 0-th column of the i-th column group is set to be R_(i,0) ⁽⁰⁾, R_(i,0) ⁽¹⁾, . . . , R_(i,0) ^((D) ^(i) ⁻¹⁾, an index R_(i,j) ^((k)) of a row in which a k-th 1 is positioned in a j-th column in the i-th column group is determined based on following Equation 5.

R _(i,j) ^((k)) R _(i,(j-1)) ^((k)) +Q _(ldpc) mod(N _(inner) −K _(ldpc))  (5)

In above Equation 5, k=0, 1, 2, . . . , D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; j=1, 2, . . . , M−1.

Meanwhile, above Equation 5 may be represented like following Equation 6.

R _(i,j) ^((k))=(R _(i,0) ^((k))+(j mod M)×Q _(ldpc))mod(N _(inner) −N _(ldpc))  (6)

In above Equation 6, k=0, 1, 2, . . . , D_(i)−1; i=0, 1, . . . , K_(ldpc)/M−1; j=1, 2, . . . , M−1. In above Equation 6, since j=1, 2, . . . , M−1, (mod M) may be considered as j.

In these Equations, J represents the index of the row in which the k-th 1 is positioned in the j-th column in the i-th column group, the N_(inner) represents the length of the LDPC codeword, the K_(ldpc) represents the length of the information bits, the D_(i) represents the degree of the columns belonging to the i-th column group, the M represents the number of columns belonging to one column group, and the Q_(ldpc) represents the size at which each column is cyclic-shifted.

As a result, referring to the above Equations, if a R_(i,0) ^((k)) value is known, the index R_(i,j) ^((k)) of the row in which the k-th 1 is positioned in the j-th column of the i-th column group may be known. Therefore, when the index value of the row in which the k-th 1 is positioned in the 0-th columns of each column group is stored, the positions of the column and the row in which the 1 is positioned in the parity check matrix 30 (that is, information sub-matrix 31 of the parity check matrix 30) having the structure of FIG. 3 may be checked.

According to the foregoing rules, all the degrees of the columns belonging to the i-th column group are D_(i). Therefore, according to the foregoing rules, the LDPC code in which the information on the parity check matrix is stored may be briefly represented as follows.

For example, when the N_(inner) is 30, the K_(ldpc) is 15, and the Q_(ldpc) is 3, positional information of the row in which 1 is positioned in the 0-th columns of three column groups may be represented by sequences as following Equation 7, which may be named ‘weight-1 position sequence’.

R _(1,0) ⁽¹⁾=1,R _(1,0) ⁽²⁾=2,R _(1,0) ⁽³⁾=8,R _(1,0) ⁽⁴⁾=10,

R _(2,0) ⁽¹⁾=0,R _(2,0) ⁽²⁾=9,R _(2,0) ⁽³⁾=13,

R _(3,0) ⁽¹⁾=0,R _(3,0) ⁽²⁾=14,  (7)

In above Equation 7, R_(i,j) ^((k)) represents the indexes of the row in which the k-th 1 is positioned in the j-th column of the i-th column group.

The weight-1 position sequences as above Equation 7 representing the index of the row in which 1 is positioned in the 0-th columns of each column group may be more briefly represented as following Table 2.

TABLE 2   1 2 8 10 0 9 13 0 1 4

Above Table 2 represents positions of elements having 1 value in the parity check matrix and the i-th weight-1 position sequence is represented by the indexes of the row in which 1 is positioned in the 0-th column belonging to the i-th column group.

The information sub-matrix 31 of the parity check matrix according to the exemplary embodiment described above may be defined based on following Table 3.

Here, following Table 3 represents the indexes of the row in which 1 is positioned in the 0-th column of the i-th column group in the information sub-matrix 31. That is, the information sub-matrix 31 is formed of a plurality of column groups each including M columns and the positions of is in the 0-th columns of each of the plurality of column groups may be defined as following Table 3.

For example, when the length N_(inner) of the LDPC codeword is 16200, the code rate is 6/15, and the M is 360, the indexes of the row in which 1 is positioned in the 0-th column of the i-th column group in the information sub-matrix 31 are as following Table 3.

TABLE 3 27 430 519 828 1897 1943 2513 2800 2640 5310 3415 4268 304

 5100 5128 5483 5928 5204 6392 6416 6802 7019 7413 7623 8212 8485 8724 2934 9445 9667 27 374

8 631 132

 1422 1779 2217 2270 2601 2813 3196 3582 3899 3908 3948 4463 4953 3120 9809 5988 6478 6604 7096 7673 7735 7795 8925 9613 9670 27 370 612 852 930 2030 1326 1521 1606 2128 2748 2809 3254 3413 3623 3742 3752 4817 489

 5300 5687 6

30 6900 6232 6491 6621 6850 7304 8542 8634 990 1753 7635 3540 933 1415

636 5745 27 6562 3707 9236 2342 8632 95

0 9615 260 1092

38 6050 15

 3750 4847 7726 4610 6580 4506 3892 2512 2974 4914 9348 1461 4021 5060

0

1736 2383

63 8306 1

 

422 7067 19

 8998 9422 1495 2931 5052 2

 1050 6235 16 4232 6364

indicates data missing or illegible when filed

According to another exemplary embodiment, a parity check matrix in which an order of indexes in each sequence corresponding to each column group in above Table 3 is changed is considered as a same parity check matrix for an LDPC code as the above described parity check matrix is another example of the inventive concept.

According to still another exemplary embodiment, a parity check matrix in which an array order of the sequences of the column groups in above Table 3 is changed is also considered as a same parity check matrix as the above described parity check matrix in that they have a same algebraic characteristics such as cyclic characteristics and degree distributions on a graph of a code.

According to yet another exemplary embodiment, a parity check matrix in which a multiple of Q_(ldpc) is added to all indexes of a sequence corresponding to column group in above Table 3 is also considered as a same parity check matrix as the above described parity check matrix in that they have a same cyclic characteristics and degree distributions on the graph of the code. Here, it is to be noted that when a value obtained by adding the multiple of Q_(ldpc) to a given sequence is equal to or more than N_(inner)−K_(ldpc), the value needs to be changed into a value obtained by performing a modulo operation on the N_(inner)−K_(ldpc) and then applied.

Meanwhile, if the position of the row in which 1 is positioned in the 0-th column of the i-th column group in the information sub-matrix 31 as shown in above Table 3 is defined, it may be cyclic-shifted by Q_(ldpc), and thus, the position of the row in which 1 is positioned in other columns of each column group may be defined.

For example, as shown in above Table 3, since the sequence corresponding to the 0-th column of the 0-th column group of the information sub-matrix 31 is “27 430 519 828 1897 1943 2513 2600 2640 3310 3415 4266 5044 5100 5328 5483 5928 6204 6392 6416 6602 7019 7415 7623 8112 8485 8724 8994 9445 9667”, in the 0-th column of the 0-th column group in the information sub-matrix 31, 1 is positioned in a 27-th row, a 430-th row, a 519-th-row, . . . .

In this case, since Q_(ldpc)(N_(inner)−K_(ldpc))/M=(16200−6480)/360=27, the indexes of the row in which 1 is positioned in the first column of the 0-th column group may be 54(=27+27), 457(=430+27), 546(=519+27), . . . , 81(=54+27), 484(=457+27), 573(=546+27) . . . .

By the above scheme, the indexes of the row in which 1 is positioned in all the rows of each column group may be defined.

Hereinafter, the method for performing the LDPC encoding based on the parity check matrix 30 as illustrated in FIG. 3 will be described.

First, information bits to be encoded are set to be i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, and code bits output from the LDPC encoding are set to be c₀, c₁, . . . , c_(N) _(ldpc) ⁻¹.

Further, since the LDPC code is systematic, for k (0≤k<K_(ldpc)−1), c_(k) is set to be i_(k). Meanwhile, the remaining code bits are set to be p_(k):=c_(k+k) _(ldpc) .

Hereinafter, a method for calculating parity bits p_(k) will be described.

Hereinafter, q(i, j, 0) represents a j-th entry of an i-th row in an index list as above Table 3, and q(i, j, l) is set to be q(i, j, l)=q(i, j, 0)+Q_(ldpc)×1 (mod N_(inner)−K_(ldpc)) for 0<i<360. Meanwhile, all the accumulations may be realized by additions in a Galois field (GF) (2). Further, in above Table 3, since the length of the LDPC codeword is 16200 and the code rate is 6/15, the Q_(ldpc) is 27.

Meanwhile, when the q(i,j,0) and the q(i,j,1) are defined as above, a process of calculating the parity bit is as follows.

Step 1) The parity bits are initialized to ‘0’. That is, p_(k)=0 for 0≤k<N_(inner)−K_(ldpc).

Step 2) For all k values of 0≤k<K_(ldpc), i and 1 are set to be i:=└k/360┘ and 1:=k (mod 360). Here, └x┘ is a maximum integer which is not greater than x.

Next, for all i, i_(k) is accumulated in p_(q(i,j,1)). That is, p_(q(i,0,1))=p_(q(i,0,1))+i_(k), p_(q(i,1,1))=p_(q(i,1,1))+i_(k), p_(q(i,2,1))=p_(q(i,2,1))+i_(k), . . . , p_(q(i,w(i)-1,1))=p_(q(i,w(i)-1,1))+i_(k) are calculated.

Here, w(i) represents the number of the values (elements) of the i-th row in the index list as above Table 3 and represents the number of is of the column corresponding to i_(k) in the parity check matrix. Further, in above Table 3, the q(i, j, 0) which is the j-th entry of the i-th row is the index of the parity bit and represents the position of the row in which 1 is positioned in the column corresponding to the i_(k) in the parity check matrix.

In detail, in above Table 3, the q(i,j,0) which is the j-th entry of the i-th row represents the position of the row in which 1 is positioned in the first (that is, 0-th) column of the i-th column group in the parity check matrix of the LDPC code.

The q(i, j, 0) may also be considered as the index of the parity bit to be generated by the LDPC encoding according to a method for allowing a real apparatus to implement a scheme for accumulating i_(k) in p_(q(i, j, 1)) for all i, and may also be considered as an index in another form when another encoding method is implemented. However, this is only one example, and therefore, it is apparent to obtain an equivalent result to the LDPC encoding result which may be obtained from the parity check matrix of the LDPC code which may basically be generated based on the q(i, j, 0) values of above Table 3 whatever the encoding scheme is applied.

Step 3) The parity bit p_(k) is calculated by calculating p_(k)=p_(k)+p_(k-1) for all k satisfying 0<k<N_(inner)−K_(ldpc).

Accordingly, all code bits c₀, c₁, . . . , c_(N) _(ldpc) ⁻¹ may be obtained.

As a result, the parity bits may be calculated by the above scheme. However, this is only one example and therefore the scheme for calculating the parity bits based on the parity check matrix as illustrated in FIG. 3 may be variously defined.

As such, the LDPC encoder 110 may perform the LDPC encoding based on above Table 3 to generate the LDPC codeword.

In detail, the LDPC encoder 110 may perform the LDPC encoding on 6480 input bits, that is, the LDPC information bits at the code rate of 6/15 based on above Table 3 to generate 9720 LDPC parity bits and output the LDPC parity bits and the LDPC codeword including the LDPC parity bits. In this case, the LDPC codeword may be formed of 16200 bits.

As described above, the LDPC encoder 110 may encode the input bits at various code rates to generate the LDPC codeword formed of the input bits and the LDPC parity bits.

The repeater 120 selects at least some bits from the LDPC codeword formed of the input bits and the LDPC parity bits, and adds the selected bits after the input bits. That is, the repeater 120 adds at least some bits of the LDPC codeword after the input bits so that these bits are transmitted while being repeated in the current frame, thereby repeating these bits in the LDPC codeword. Further, the repeater 120 may output the repeated LDPC codeword, that is, LDPC codeword bits including the repeated bits (alternatively referred to as an LDPC codeword with repetition) to the puncturer 130.

In detail, the repeater 120 may select a predetermined number of bits from the LDPC parity bits, and add the selected bits after the LDPC information bits. Therefore, the selected bits are repeated after the LDPC information bits and are positioned between the LDPC information bits and the LDPC parity bits.

Therefore, since the predetermined number of bits within the LDPC codeword may be repeated and additionally transmitted to the receiver 200, the foregoing operation may be referred to as repetition. Further, the bits repeated in the LDPC codeword, that is, the bits added after the LDPC information bits depending on the repetition may be referred to as repetition bits or repeated bits.

For this purpose, the repeater 120 may calculate the number of bits to be added, that is, the number of bits to be repeated based on the number of bits other than padded zero bits, if any, in the input bits.

In detail, since, as described above, the input bits include the outer encoded bits and the padded zero bits, the repeater 120 may calculate the number of bits to be repeated based on the bits other than the zero bits padded in the input bits, that is, the outer encoded bits.

That is, the repeater 120 may calculate the number of bits to be repeated based on the number of outer encoded bits. Here, when the outer encoding is performed by the BCH encoding, the repeater 120 may calculate the number of bits to be repeated based on the number of BCH encoded bits.

In detail, the repeater 120 may calculate the number N_(repeat) of repetition bits, that is, the number of bits to be repeated, which are additionally transmitted in the LDPC codeword with repetition based on following Equation 8.

N _(repeat)=2×└C×N _(outer) ┘+D  (8)

With respect to Equation 8, └x┘ represents a maximum integer which is not greater than x, N_(outer) represents the number of outer-encoded bits. Here, when the outer encoding is performed by the BCH encoding, the N_(outer) represents the number of BCH encoded bits.

Further, C and D are a preset constant. For example, C may be a fixed number and D may be an even integer.

For example, when N_(outer)=368, K_(sig)=200, K_(ldpc)=3240, N_(ldpc_parity)=12960, then C=0 and D=3672, and when N_(outer) is in a range of 568 to 2520, K_(sig) is in a ranged of 400 to 2352, K_(ldpc)=3240, N_(ldpc_parity)=12960, then C=61/16 and D=−508.

However, the information bits may not be outer-encoded, or may be encoded by an encoding scheme other than the BCH encoding. In this case, the repeater 120 may calculate the number of bits to be repeated based on the number of information bits or the number of encoded bits generated by the encoding scheme other than the BCH encoding.

Further, the repeater 120 may select bits as many as the calculated number from the LDPC parity bits and add the selected bits to the input bits. That is, the repeater 120 may select bits as many as the calculated number from the LDPC parity bits and add the selected bits after the LDPC information bits.

In detail, when the calculated number of bits is equal to or less than the number of LDPC parity bits, the repeater 120 may select bits as many as the calculated number from a first LDPC parity bit and add the selected bits after the input bits.

That is, the repeater 120 may select LDPC parity bits as many as the calculated number from a front portion of the LDPC parity bits and add the selected bits after the input bits.

For example, when N_(repeat) is equal to or less than N_(ldpc_parity), that is, when N_(repeat)≤N_(ldpc_parity), as illustrated in FIG. 4, the repeater 120 may select a first N_(repeat) bits (p₀, p₁, . . . , p_(N) _(repeat) ⁻¹) of LDPC parity bits (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹), and add the selected N_(repeat) bits after LDPC information bits (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹).

Therefore, the first N_(repeat) bits of the LDPC parity bits are added to the LDPC information bits later, and the N_(repeat) bits are positioned between the LDPC information bits and the LDPC parity bits like (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) ⁻¹, p₀, p₁, . . . p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹).

Meanwhile, when the calculated number of bits is greater than the number of LDPC parity bits, the repeater 120 may select all the LDPC parity bits and add the selected LDPC parity bits as a part of repetition bits after the input bits, and additionally select bits as many as the number obtained by subtracting the number of LDPC parity bits from the calculated number of bits from the first LDPC parity bit and add the additionally selected bits after the earlier added LDPC parity bits.

In this case, the repeater 120 may select bits as many as the number obtained by subtracting the number of LDPC parity bits from the calculated number of bits from the first LDPC parity bit of the existing LDPC parity bits, that is, the LDPC parity bits generated by the LDPC encoding, not from the LDPC parity bits added to the input bits, and add the additionally selected bits after the earlier added LDPC parity bits. That is, the repeater 120 may select LDPC parity bits as many as the calculated number from the front portion of the LDPC parity bits generated by the LDPC encoding, and add the additionally selected bits after the earlier added LDPC parity bits.

For example, when N_(repeat) is greater than N_(ldpc_parity), that is, when N_(repeat)>N_(ldpc_parity), as illustrated in FIG. 5, the repeater 120 selects N_(ldpc_parity) LDPC parity bits (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹) and adds the selected N_(ldpc_parity) bits, as a part of repetition bits, after the LDPC information bits (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹). Further, the repeater 120 may additionally select N_(repeat)−N_(ldpc_parity) bits (p₀, p₁, . . . , p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹) from the first bit of the LDPC parity bits and add the additionally selected N_(repeat)−N_(ldpc_parity) bits after the earlier added N_(ldpc_parity) LDPC parity bits.

Therefore, N_(ldpc_parity) LDPC parity bits may be added to the LDPC information bits and N_(repeat)−N_(ldpc_parity) bits from the first bit of the LDPC parity bits may be additionally added to the earlier added N_(ldpc_parity) LDPC parity bits.

Therefore, N_(repeat) bits are positioned between the LDPC information bits and the LDPC parity bits, like (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹, p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹).

Meanwhile, the foregoing example describes that the repetition bits are added after the input bits, which is only an example. According to another exemplary embodiment, the repeater 120 may add the repetition bits after the LDPC parity bits.

For example, when the N_(repeat) is equal to or less than N_(ldpc_parity), that is, when N_(repeat)≤N_(ldpc_parity), as illustrated in FIG. 6, the repeater 120 may select N_(repeat) bits (p₀, p₁, . . . , p_(N) _(repeat) ⁻¹) from the first bit of the LDPC parity bits (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹) and add the selected N_(repeat) bits after the LDPC parity bits.

Therefore, N_(repeat) bits of the LDPC parity bits are added to the LDPC parity bits and positioned after the LDPC parity bits like (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) ⁻¹).

As another example, when N_(repeat) is greater than N_(ldpc_parity), that is, when N_(repeat)>N_(ldpc_parity), as illustrated in FIG. 7, the repeater 120 selects N_(ldpc_parity) LDPC parity bits (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹) and adds the selected N_(ldpc_parity) bits after LDPC parity bits. Further, the repeater 120 may additionally select N_(repeat)−N_(ldpc_parity) bits (p₀, p₁, . . . , p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹) from the first bit of the LDPC parity bits and add the additionally selected N_(repeat)-N_(ldpc_parity) bits after the earlier added N_(ldpc_parity) LDPC parity bits.

Therefore, N_(ldpc_parity) LDPC parity bits may be added to the LDPC parity bits as a part of repetition bits, and N_(repeat)−N_(ldpc_parity) bits of the LDPC parity bits may be additionally added as the other part of the repetition bits to the earlier added N_(ldpc_parity) LDPC parity bits.

Therefore, N_(repeat) bits like(i₀, i₁, . . . , p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹) are positioned after the LDPC parity bits.

The foregoing example describes that bits are sequentially selected from the front portion of LDPC parity bits, which is only an example. According to another exemplary embodiment, the repeater 120 may select bits from a back portion or a middle portion of the LDPC parity bits.

The foregoing example describes that bits are selected only from LDPC parity bits in an LDPC codeword formed of LDPC information bits and the LDPC parity bits, which is only an example. According to another exemplary embodiment, the repeater 120 may select bits from the LDPC information bits or some bits from the LDPC information bits and the rest of the bits from the LDPC parity bits to generate the repetition bits.

The puncturer 130 may puncture some bits from LDPC parity bits.

Here, the puncturing means that some of the LDPC parity bits are not transmitted to the receiver 200. In this case, the puncturer 130 may remove the punctured LDPC parity bits or output only the remaining bits other than the punctured LDPC parity bits in the LDPC codeword.

In detail, the puncturer 130 may puncture a predetermined number of bits at a back portion of the LDPC parity bits. That is, the puncturer 130 may puncture the predetermined number of bits from a last bit of the LDPC parity bits. For example, the puncturer 130 may sequentially puncture N_(punc) bits from the last bit of the LDPC parity bits.

However, the puncturer 130 may not puncture the repeated LDPC parity bits but may puncture a predetermined number of bits from a last bit of LDPC parity bits which are generated by LDPC encoding.

In detail, an LDPC codeword with repetition formed of LDPC information bits, repeated LDPC parity bits, i.e., repetition bits, and LDPC parity bits generated by LDPC encoding, and the puncturer 130 may puncture not the repetition bits but puncture a predetermined number of bits from the last bit of the LDPC parity bits generated by the LDPC encoding.

That is, in the foregoing example, when N_(repeat) LDPC parity bits are added by repetition, the puncturer 130 may puncture N_(punc) bits not from the N_(repeat) LDPC parity but from the last bit of N_(ldpc_parity) LDPC parity bits generated by the LDPC encoding.

Hereinafter, puncturing methods according to various exemplary embodiments will be described with reference to the accompanying FIGS. 8 to 11.

First, as illustrated in FIG. 4, it is assumed that N_(repeat) LDPC parity bits are added after LDPC information bits by repetition.

In this case, as illustrated in FIG. 8, the puncturer 130 may puncture N_(punc) bits from a last bit of N_(ldpc_parity) LDPC parity bits.

Therefore, the number of LDPC parity bits in a repeated and punctured LDPC codeword is N_(ldpc_parity)+N_(repeat)−N_(punc) and may be represented by (p₀, p₁, . . . , p_(N) _(repeat) ⁻¹, p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) _(−N) _(punc) ⁻¹).

As another example, as illustrated in FIG. 5, it is assumed that N_(repeat) LDPC parity bits are added by repetition after LDPC information bits and before LDPC parity bits generated by LDPC encoding.

In this case, as illustrated in FIG. 9, the puncturer 130 may puncture N_(punc) bits from a last bit of N_(ldpc_parity) LDPC parity bits generated by the LDPC encoding.

Therefore, the number of LDPC parity bits in a repeated and punctured LDPC codeword is N_(ldpc_parity)+N_(repeat)−N_(punc) and may be represented by (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹, p₀, p₁, p_(N) _(ldpc) _(−K) _(ldpc) _(−N) _(punc) ⁻¹).

As another example, as illustrated in FIG. 6, it is assumed that N_(repeat) LDPC parity bits are added by repetition after LDPC parity bits generated by LDPC encoding.

In this case, as illustrated in FIG. 10, the puncturer 130 may puncture N_(punc) bits from a last bit of N_(ldpc_parity) LDPC parity bits.

Therefore, the number of LDPC parity bits in a repeated and punctured LDPC codeword is N_(ldpc_parity)+N_(repeat)−N_(punc) and may be represented by (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) _(−N) _(punc) ⁻¹, p₀, p₁, . . . , p_(N) _(repeat) ⁻¹).

As another example, as illustrated in FIG. 7, it is assumed that N_(repeat) LDPC parity bits are added by repetition after LDPC parity bits generated by LDPC encoding.

In this case, as illustrated in FIG. 11, the puncturer 130 may puncture N_(punc) bits of from a last bit N_(ldpc_parity) LDPC parity bits generated by LDPC encoding.

Therefore, the number of LDPC parity bits in a repeated and punctured LDPC codeword is N_(ldpc_parity)+N_(repeat)−N_(punc) and may be represented by (p₀, p₁, . . . , p_(N) _(ldpc) _(−K) _(ldpc) _(−N) _(punc) ⁻¹, p₀, p₁, p_(N) _(ldpc) _(−K) _(ldpc) ⁻¹, p₀, p₁, p_(N) _(repeat) _(−N) _(ldpc_parity) ⁻¹).

The foregoing example describes that repetition is performed, and then, puncturing is performed, which is only an example. According to another exemplary embodiment, an order of the repeater 120 and the puncturer 130 may be changed according to a system.

For example, the puncturer 130 may perform puncturing while physically deleting bits from a memory but generally, since bit values physically remain in the memory for a predetermined operation period, the same results may be output even though the puncturing may be first applied and the repeater 120 properly performs the repetition thereafter.

Meanwhile, the transmitter 100 may transmit a repeated and punctured LDPC codeword to the receiver 200.

In detail, the transmitter 100 may modulate the repeated and punctured LDPC codeword bits by QPSK, map the modulated bits to constellation symbols, map the constellation symbols to a frame, and transmit the frame to the receiver 200.

According to an exemplary embodiment, when the LDPC encoder 110 performs LDPC encoding at a code rate of 3/15 based on above Table 1, the repeater 120 may perform repetition. In this case, the repeater 120 may calculate N_(repeat) using C=0, D=3672 or C=61/16, D=−508 depending on a K_(sig) value and repeat the calculated N_(repeat) bits.

However, when the LDPC encoder 110 performs the LDPC encoding at a code rate of 6/15 based on above Table 3, the repetition may be omitted. In this case, the transmitter 100 may modulate a punctured LDPC codeword by QPSK, 16-quadrature amplitude modulation (16-QAM), 64-QAM, or 256-QAM, map the modulated LDPC codeword to constellation symbols, map the constellation symbols to a frame, and transmit the frame to the receiver 200.

Meanwhile, as described above, since the information bits are the signaling including signaling information about data, the transmitter 100 may map the data to the frame along with the signaling for processing the data and transmit the mapped data to the receiver 200.

In detail, the transmitter 100 may process the data in a specific scheme to generate the constellation symbols and map the generated constellation symbols to data symbols of each frame. Further, the transmitter 100 may map the signaling for the data mapped to each frame to a preamble of the frame. For example, the transmitter 100 may map the signaling including the signaling information for the data mapped to an i-th frame to the i-th frame.

As a result, the receiver 200 may use the signaling acquired from the frame to acquire and process the data from the frame.

One reason of performing the above-described repetition according to the exemplary embodiments is as follows.

The repetition may be used to acquire a diversity gain, but an additional coding gain may not be acquired.

As a simple example, if a codeword having a predetermined length is transmitted using the repetition, a same signal is transmitted twice, and thus, an effect that an amplitude of a received signal becomes twice, that is, a 3 dB gain is obtained. In this case, since a codeword is transmitted at different times, a diversity gain is acquired. However, if an additional parity in addition to an original parity included in the codeword is generated and transmitted by a predetermined length, decoding complexity is slightly increased. Nonetheless, in addition to the diversity gain, a coding gain is obtained. For this reason, in terms of performance, instead of the repetition, a method for transmitting an additional parity may be used.

According to the present exemplary embodiments, a method of transmitting information bits is performed such that a parity having a predetermined length is repeatedly transmitted, and at least a part of the parity is punctured. This method can be implemented by a distribution of 1 within the sub-matrix C in the parity check matrix 20 illustrated in FIG. 2.

In FIG. 2, the sub-matrices B and D each are a parity matrix. In the sub-matrix B, except for one column, the number of is in each column is two (2). The sub-matrix D has an identify matrix form in which the number of 1s is one (1) in all columns and rows. In this case, the repetition may be efficient or inefficient depending on the distribution of 1 in the sub-matrix C.

Generally, the identity matrix like the sub-matrix D means single parity-check codes generating a single parity-check bit for bits corresponding to the sub-matrix C in generating a parity. Since one single parity check bit does not have an error correction capability, it may provide excellent performance only when a plurality of single parity check codes are concatenated with a channel code having a proper error correction capability. Therefore, when a single parity check bit portion is punched, even though punched bits are additionally transmitted, its effect may be insignificant if there is no appropriate connection with a channel code portion having the error correction capability.

For example, in FIG. 2, parity bits corresponding to a front portion of the sub-matrix D are relatively in a stable connection with a partial parity check matrix formed of the sub-matrices A and B having the error correction capability depending on the distribution of 1s in the sub-matrix C. On the other hand, in parity bits corresponding to a back portion of the sub-matrix D, the distribution of is directly connected to the sub-matrices A and B depending on the distribution of is in the sub-matrix C is non-uniform. In this case, transmitting parity bits corresponding to the sub-matrix B more stably connected or parity bits corresponding to the front portion of the sub-matrix D by repetition may provide better performance than transmitting parity bits corresponding to the back portion of the sub-matrix D.

Thus, the repetition of parity bits using the parity check matrix 20 in which (A, B) and (C, D) are concatenated as illustrated in FIG. 2 depending on the distribution of is in the sub-matrix C may provide better performance.

The above description is described based on a simple example to help better understanding of the present exemplary embodiments. A parity check matrix may be subdivided depending on the distribution of is in the sub-matrix C, a length of repetition bits, and a length of punctured parity bits and a density evolution analysis method is applied, thereby deriving a theoretical prediction value for a signal to noise (SNR) ratio which provides error free communication during a channel coding process and determining whether it is efficient to apply repetition based on the theoretically predicted SNR values. That is, a code to which the repetition is to be applied and a code to which the repetition is not to be applied are determined during the above process according to an applied channel coding.

The repetition is efficiently determined in a case of the code rate 3/15 LDPC code corresponding to above Table 1, and thus, an appropriate repetition method is applied, which includes a process of transmitting the repetition bits and a process of puncturing parity bits. On the other hand, it is determined that the repetition is not efficient in a case of the code rate 6/15 LDPC code corresponding to above Table 3, and thus, the repetition may not be applied.

Meanwhile, according to an exemplary embodiment, the information bits may be implemented by L1-basic signaling and L1-detail signaling. Therefore, the transmitter 100 may perform the repetition on the L1-basic signaling and the L1-detail signaling by using the foregoing method and transmit these signalings to the receiver 200.

Here, the L1-basic signaling and the L1-detail signaling may be signaling defined in an Advanced Television System Committee (ATSC) 3.0 standard.

In detail, there are seven (7) modes of processing the L1-basic signaling. The transmitter 100 according to the exemplary embodiments may perform repetition according to the foregoing method when an L1-basic mode 1 of the seven modes processes the L1-basic signaling.

Further, there are seven modes of processing the L1-detail signaling is also divided into seven (7). The transmitter 100 according to the exemplary embodiment may perform repetition according to the foregoing method when an L1-detail mode 1 of the 7 modes processes the L1-detail signaling.

The transmitter 100 may process each of the L1-basic signaling and the L1-detail signaling in other modes using a specific scheme, in addition to the L1-basic mode 1 and the L1-detail mode 1, and transmit the processed signalings to the receiver 200.

A method for processing the L1-basic signaling and the L1-detail signaling will be described below.

The transmitter 100 may map the L1-basic signaling and the L1-detail signaling to a preamble of a frame and map data to data symbols of the frame, and transmit the frame to the receiver 200.

Referring to FIG. 12, the frame may be configured of three parts, that is, a bootstrap part, a preamble part, and a data part.

The bootstrap part is used for initial synchronization and provides a basic parameter required for the receiver 200 to decode the L1 signaling. Further, the bootstrap part may include information about a mode of processing the L1-basic signaling at the transmitter 100, that is, information about a mode the transmitter 100 uses to process the L1-basic signaling.

The preamble part includes the L1 signaling, and may be configured of two parts, that is, the L1-basic signaling and the L1-detail signaling.

Here, the L1-basic signaling may include information about the L1-detail signaling, and the L1-detail signaling may include information about data. Here, the data is broadcasting data for providing broadcasting services and may be transmitted through at least one physical layer pipes (PLPs).

In detail, the L1-basic signaling includes information required for the receiver 200 to process the L1-detail signaling. This information includes, for example, information about a mode of processing the L1-detail signaling at the transmitter 100, that is, information about a mode the transmitter 100 uses to process the L1-detail signaling, information about a length of the L1-detail signaling, information about an additional parity mode, that is, information about a K value used for the transmitter 100 to generate additional parity bits using an L1B_L1_Detail_additional_parity_mode (here, when the L1B_L1_Detail_additional_parity_mode is set as ‘00’, K=0 and the additional parity bits are not used), and information about a length of total cells. Further, the L1-basic signaling may include basic signaling information about a system including the transmitter 100 such as a fast Fourier transform (FFT) size, a guard interval, and a pilot pattern.

Further, the L1-detail signaling includes information required for the receiver 200 to decode the PLPs, for example, start positions of cells mapped to data symbols for each PLP, PLP identifier (ID), a size of the PLP, a modulation scheme, a code rate, etc.

Therefore, the receiver 200 may acquire frame synchronization, acquire the L1-basic signaling and the L1-detail signaling from the preamble, and receive service data required by a user from data symbols using the L1-detail signaling.

The method for processing the L1-basic signaling and the L1-detail signaling will be described below in more detail with reference to the accompanying drawings.

FIGS. 13 and 14 are block diagrams for describing a detailed configuration of a transmitter according to an exemplary embodiment.

In detail, as illustrated in FIG. 13, to process the L1-basic signaling, the transmitter 100 may include a scrambler 211, a BCH encoder 212, a zero padder 213, an LDPC encoder 214, a parity permutator 215, a repeater 216, a puncturer 217, a zero remover 218, a bit demultiplexer 219, and a constellation mapper 221.

Further, as illustrated in FIG. 14, to process the L1-detail signaling, the transmitter 100 may include a segmenter 311, a scrambler 312, a BCH encoder 313, a zero padder 314, an LDPC encoder 315, a parity permutator 316, a repeater 317, a puncturer 318, an additional parity generator 319, a zero remover 321, bit demultiplexers 322 and 323, and constellation mappers 324 and 325.

Here, the components illustrated in FIGS. 13 and 14 are components for performing encoding and modulation on the L1-basic signaling and the L1-detail signaling, which is only one example. According to another exemplary embodiments, some of the components illustrated in FIGS. 13 and 14 may be omitted or changed, and other components may also be added. Further, positions of some of the components may be changed. For example, the positions of the repeaters 216 and 317 may be disposed after the puncturers 217 and 318, respectively.

Meanwhile, the LDPC encoder 315, the repeater 317, and the puncturer 318 illustrated in FIG. 14 may perform the operations performed by the LDPC encoder 110, the repeater 120, and the puncturer 130 illustrated in FIG. 1, respectively.

Meanwhile, in describing FIGS. 13 and 14, for convenience, components for performing common functions will be described together.

The L1-basic signaling and the L1-detail signaling may be protected by concatenation of a BCH outer code and an LDPC inner code. However, this is only one example. Therefore, as outer encoding performed before inner encoding in the concatenated coding, another encoding such as CRC encoding in addition to the BCH encoding may be used. Further, the L1-basic signaling and the L1-detail signaling may be protected only by the LDPC inner code without the outer code.

First, the L1-basic signaling and the L1-detail signaling may be scrambled. Further, the L1-basic signaling and the L1-detail signaling are BCH encoded, and thus, BCH parity check bits of the L1-basic signaling and the L1-detail signaling generated from the BCH encoding may be added to the L1-basic signaling and the L1-detail signaling, respectively. Further, the concatenated signaling and the BCH parity check bits may be additionally protected by a shortened and punctured 16K LDPC code.

Meanwhile, to provide various robustness level appropriate for a wide SNR range, a protection level of the L1-basic signaling and the L1-detail signaling may be divided into seven modes. That is, the protection level of the L1-basic signaling and the L1-detail signaling may be divided into the seven modes based on an LDPC code, a modulation order, shortening/puncturing parameters (that is, a ratio of the number of bits to be punctured to the number of bits to be shortened), and the number of bits to be basically punctured (that is, the number of bits to be basically punctured when the number of bits to be shortened is 0). In each mode, at least one different combination of the LDPC code, the modulation order, the constellation, and the shortening/puncturing pattern may be used.

Meanwhile, by which mode the transmitter 100 processes the signaling may be set in advance depending on a system. Therefore, the transmitter 100 may determine parameters (for example, modulation and code rate (ModCod) for each mode, parameter for the BCH encoding, parameter for the zero padding, shortening pattern, code rate/code length of the LDPC code, group-wise interleaving pattern, parameter for repetition, parameter for puncturing, and modulation scheme, etc.) for processing the signaling depending on the set mode, and may process the signaling based on the determined parameters and transmit the processed signaling to the receiver 200. For this purpose, the transmitter 100 may pre-store the parameters for processing the signaling depending on the mode.

Modulation and code rate configurations (ModCod configurations) for the seven modes for processing the L1-basic signaling and the seven modes for processing the L1-detail signaling are shown in following Table 4. The transmitter 100 may encode and modulate the signaling based on the ModCod configurations defined in following Table 4 according to a corresponding mode. That is, the transmitter 100 may determine an encoding and modulation scheme for the signaling in each mode based on following Table 4, and may encode and modulate the signaling according to the determined scheme. In this case, even when modulating the L1 signaling by the same modulation scheme, the transmitter 100 may also use different constellations.

TABLE 4 Code Signaling FEC Type K_(sig) Length Code Rate Constellation L1-Basic Mode 1 200 16200 3/15 QPSK Mode 2 (Type A) QPSK Mode 3 QPSK Mode 4 NUC_16-QAM Mode 5 NUC_64-QAM Mode 6 NUC_256-QAM Mode 7 NUC_256-QAM L1-Detail Mode 1 400 - 2352 QPSK Mode 2 400 - 3072 QPSK Mode 3 400 - 6312 6/15 QPSK Mode 4 (Type B) NUC_16-QAM Mode 5 NUC_64-QAM Mode 6 NUC_256-QAM Mode 7 NUC_256-QAM

Meanwhile, in above Table 4, K_(sig) represents the number of information bits for a coded block. That is, since the L1 signaling bits having a length of K_(sig) are encoded to generate the coded block, a length of the L1 signaling in one coded block becomes K_(sig). Therefore, the L1 signaling bits having the size of K_(sig) may be considered as corresponding to one LDPC coded block.

Referring to above Table 4, the K_(sig) value for the L1-basic signaling is fixed to 200. However, since the amount of L1-detail signaling bits varies, the K_(sig) value for the L1-detail signaling varies.

In detail, in a case of the L1-detail signaling, the number of L1-detail signaling bits varies, and thus, when the number of L1-detail signaling bits is greater than a preset value, the L1-detail signaling may be segmented to have a length which is equal to or less than the preset value.

In this case, each size of the segmented L1-detail signaling blocks (that is, segment of the L1-detail signaling) may have the K_(sig) value defined in above Table 4. Further, each of the segmented L1-detail signaling blocks having the size of K_(sig) may correspond to one LDPC coded block.

However, when the number of L1-detail signaling bits is equal to or less than the preset value, the L1-detail signaling is not segmented. In this case, the size of the L1-detail signaling may have the K_(sig) value defined in above Table 4. Further, the L1-detail signaling having the size of K_(sig) may correspond to one LDPC coded block.

Hereinafter, a method for segmenting L1-detail signaling will be described in detail.

The segmenter 311 segments the L1-detail signaling. In detail, since the length of the L1-detail signaling varies, when the length of the L1-detail signaling is greater than the preset value, the segmenter 311 may segment the L1-detail signaling to have the number of bits which are equal to or less than the preset value and output each of the segmented L1-detail signalings to the scrambler 312.

However, when the length of the L1-detail signaling is equal to or less than the preset value, the segmenter 311 does not perform a separate segmentation operation.

Meanwhile, a method for segmenting, by the segmenter 311, the L1-detail signaling is as follows.

The amount of L1-detail signaling bits varies and mainly depends on the number of PLPs. Therefore, to transmit all bits of the L1-detail signaling, at least one forward error correction (FEC) frame is required. Here, an FEC frame may represent a form in which the L1-detail signaling is encoded, and thus, parity bits according to the encoding are added to the L1-detail signaling.

In detail, when the L1-detail signaling is not segmented, the L1-detail signaling is BCH-encoded and LDPC encoded to generate one FEC frame, and therefore, one FEC frame is required for the L1-detail signaling transmission. On the other hand, when the L1-detail signaling is segmented into at least two, at least two segmented L1-detail signalings each are BCH encoded and LDPC encoded to generate at least two FEC frames, and therefore, at least two FEC frames are required for the L1-detail signaling transmission.

Therefore, the segmenter 311 may calculate the number N_(L1D_FECFRAME) of FEC frames for the L1-detail signaling based on following Equation 9. That is, the number N_(L1D_FECFRAME) of FEC frames for the L1-detail signaling may be determined based on following Equation 9.

$\begin{matrix} {N_{L\; 1{D\_{FECFRAME}}} = \left\lceil \frac{K_{L\; 1{D\_{ex}}{\_{pad}}}}{K_{seg}} \right\rceil} & (9) \end{matrix}$

In above Equation 9, represents a minimum integer which is equal to or greater than x.

Further, K_(L1D_ex_pad) represents the length of the L1-detail signaling other than L1 padding bits as illustrated in FIG. 15 and may be determined by a value of an L1B_L1_Detail_size_bits field included in the L1-basic signaling.

Further, K_(seg) represents a threshold number for segmentation defined based on the number K_(ldpc) of information bits input to the LDPC encoder 315, that is, the LDPC information bits. Further, K_(seg) may be defined based on the number of BCH parity check bits of a BCH code and a multiple value of 360.

Meanwhile, K_(seg) is determined such that, after the L1-detail signaling is segmented, the number K_(sig) of information bits in the coded block is set to be equal to or less than K_(ldpc)−M_(outer). In detail, when the L1-detail signaling is segmented based on K_(seg), since the length of segmented L1-detail signaling does not exceed K_(seg), the length of the segmented L1-detail signaling is set to be equal to or less than K_(ldpc)−M_(outer) when K_(seg) is set like in Table 5 as following.

Here, M_(outer) and K_(ldpc) are as following Tables 6 and 7. Meanwhile, for sufficient robustness, the K_(seg) value for the L1-detail signaling mode 1 may be set to be K_(ldpc)−M_(outer)−720.

Meanwhile, K_(seg) for each mode of the L1-detail signaling may be defined as following Table 5. In this case, the segmenter 311 may determine K_(seg) according to a corresponding mode as shown in following Table 5.

TABLE 5 L1-Detail K_(seg) Mode 1 2352 Mode 2 3072 Mode 3 6312 Mode 4 Mode 5 Mode 5 Mode 7

Meanwhile, an entire L1-detail signaling may be formed of L1-detail signaling and L1 padding bits.

In this case, the segmenter 311 may calculate a length of an L1_PADDING field for the L1-detail signaling, that is, the number L1D_PAD of the L1 padding bits based on following Equation 10.

However, calculating K_(L1D_PAD) based on following Equation 10 is only one example. That is, the segmenter 311 may calculate the length of the L1_PADDING field for the L1-detail signaling, that is, the number K_(L1D_PAD) of the L1 padding bits based on K_(L1D_ex_pad) and N_(L1D_FECFRAME) values. As one example, the K_(L1D_PAD) value may be obtained based on following Equation 10. That is, following Equation 10 is only one example of a method for obtaining a K_(L1D_PAD) value, and thus, another method based on the K_(L1D_ex_pad) and N_(L1D_FECFRAME) values may be applied to obtain an equivalent result.

$\begin{matrix} {K_{L1D\_{PAD}} = {{\left\lceil \frac{K_{{L1D\_{ex}}{\_{pad}}}}{\left( {N_{L\; 1{D\_{FECFRAME}}} \times 8} \right)} \right\rceil \times 8 \times N_{L\; 1{D\_{FECFRAME}}}} - K_{{L1D\_{ex}}{\_{pad}}}}} & (10) \end{matrix}$

Further, the segmenter 311 may fill the L1_PADDING field with K_(L1D_PAD) zero bits (that is, bits having a 0 value). Therefore, as illustrated in FIG. 15, the K_(L1D_PAD) zero bits may be filled in the L1_PADDING field.

As such, by calculating the length of the L1_PADDING field and padding zero bits of the calculated length to the L1_PADDING field, the L1-detail signaling may be segmented into the plurality of blocks formed of the same number of bits when the L1-detail signaling is segmented.

Next, the segmenter 311 may calculate a final length K_(ID) of the entire L1-detail signaling including the zero padding bits based on following Equation 11.

K _(L1D) =K _(L1D_ex_pad) +K _(L1D_PAD)  (11)

Further, the segmenter 311 may calculate the number K_(sig) of information bits in each of the N_(L1D_FECFRAME) blocks based on following Equation 12.

$\begin{matrix} {K_{sig} = \frac{K_{L\; 1D}}{N_{L\; 1D\;\_\;{FECFRAME}}}} & (12) \end{matrix}$

Next, the segmenter 311 may segment the L1-detail signaling by the number of K_(sig) bits.

In detail, as illustrated in FIG. 15, when the N_(L1D_FECFRAME) is greater than 1, the segmenter 311 may segment the L1-detail signaling by the number of K_(sig) bits to segment the L1-detail signaling into the N_(L1D_FECFRAME) blocks.

Therefore, the L1-detail signaling may be segmented into N_(L1D_FECFRAME) blocks, and the number of L1-detail signaling bits in each of the N_(L1D_FECFRAME) blocks may be K_(sig). Further, each segmented L1-detail signaling is encoded. As an encoded result, a coded block, that is, an FEC frame is formed, such that the number of L1-detail signaling bits in each of the N_(L1D_FECFRAME) coded blocks may be K_(sig).

However, when the L1-detail signaling is not segmented, K_(sig)=K_(L1D_ex_pad).

Meanwhile, the segmented L1-detail signaling blocks may be encoded by a following procedure.

In detail, all bits of each of the L1-detail signaling blocks having the size K_(sig) may be scrambled. Next, each of the scrambled L1-detail signaling blocks may be encoded by concatenation of the BCH outer code and the LDPC inner code.

In detail, each of the L1-detail signaling blocks is BCH-encoded, and thus M_(outer) (=168) BCH parity check bits may be added to the K_(sig) L1-detail signaling bits of each block, and then, the concatenation of the L1-detail signaling bits and the BCH parity check bits of each block may be encoded by a shortened and punctured 16K LDPC code. Meanwhile, the details of the BCH code and the LDPC code will be described below. However, the exemplary embodiments describe only a case in which M_(outer)=168, but it is apparent that M_(outer) may be changed into an appropriate value depending on the requirements of a system.

The scramblers 211 and 312 scramble the L1-basic signaling and the L1-detail signaling, respectively. In detail, the scramblers 211 and 312 may randomize the L1-basic signaling and the L1-detail signaling, and output the randomized L1-basic signaling and L1-detail signaling to the BCH encoders 212 and 313, respectively.

In this case, the scramblers 211 and 312 may scramble the information bits by a unit of K_(sig).

That is, since the number of L1-basic signaling bits transmitted to the receiver 200 through each frame is 200, the scrambler 211 may scramble the L1-basic signaling bits by K_(sig) (=200).

Meanwhile, since the number of L1-basic signaling bits transmitted to the receiver 200 through each frame varies, in some cases, the L1-detail signaling may be segmented by the segmenter 311. Further, the segmenter 311 may output the L1-detail signaling formed of K_(sig) bits or the segmented L1-detail signaling blocks to the scrambler 312. As a result, the scrambler 312 may scramble the L1-detail signaling bits by every K_(sig) which are output from the segmenter 311.

The BCH encoders 212 and 313 perform the BCH encoding on the L1-basic signaling and the L1-detail signaling to generate the BCH parity check bits.

In detail, the BCH encoders 212 and 313 may perform the BCH encoding on the L1-basic signaling and the L1-detail signaling output from the scramblers 211 and 313, respectively, to generate the BCH parity check bits, and output the BCH-encoded bits in which the BCH parity check bits are added to each of the L1-basic signaling and the L1-detail signaling to the zero padders 213 and 314, respectively.

For example, the BCH encoders 212 and 313 may perform the BCH encoding on the input K_(sig) bits to generate the M_(outer) (that is, K_(sig)=K_(payload)) BCH parity check bits and output the BCH-encoded bits formed of N_(outer) (=K_(sig)+M_(outer)) bits to the zero padders 213 and 314, respectively.

Meanwhile, the parameters for the BCH encoding may be defined as following Table 6.

TABLE 6 Signaling FEC Type K_(sig) = K_(payload) M_(outer) N_(outer) = K_(sig) + M_(outer) L1-Basic Mode 1 200 168 368 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 L1-Detail Mode 1 400 - 2352 568 - 2520 Mode 2 400~3072 568~3240 Mode 3 400 - 6312 568 - 6480 Mode 4 Mode 5 Mode 6 Mode 7

Meanwhile, referring to FIGS. 13 and 14, it may be appreciated that the LDPC encoders 214 and 315 may be disposed after the BCH encoders 212 and 313, respectively.

Therefore, the L1-basic signaling and the L1-detail signaling may be protected by the concatenation of the BCH outer code and the LDPC inner code.

In detail, the L1-basic signaling and the L1-detail signaling are BCH-encoded, and thus, the BCH parity check bits for the L1-basic signaling are added to the L1-basic signaling and the BCH parity check bits for the L1-detail signaling are added to the L1-detail signaling. Further, the concatenated L1-basic signaling and BCH parity check bits are additionally protected by the LDPC code and the concatenated L1-detail signaling and BCH parity check bits may be additionally protected by the LDPC code.

Here, it is assumed that the LDPC code is a 16K LDPC code, and thus, in the BCH encoders 212 and 213, a systematic BCH code for N_(inner)=16200 (that is, the code length of the 16K LDPC is 16200 and an LDPC codeword generated by the LDPC encoding may be formed of 16200 bits) may be used to perform outer encoding of the L1-basic signaling and the L1-detail signaling.

The zero padders 213 and 314 pad zero bits. In detail, for the LDPC code, a predetermined number of LDPC information bits defined according to a code rate and a code length is required, and thus, the zero padders 213 and 314 may pad zero bits for the LDPC encoding to generate the predetermined number of LDPC information bits formed of the BCH-encoded bits and zero bits, and output the generated bits to the LDPC encoders 214 and 315, respectively, when the number of BCH-encoded bits is less than the number of LDPC information bits. Meanwhile, when the number of BCH-encoded bits is equal to the number of LDPC information bits, zero bits are not padded.

Here, zero bits padded by the zero padders 213 and 314 are padded for the LDPC encoding, and therefore, the padded zero bits padded are not transmitted to the receiver 200 by a shortening operation.

For example, when the number of LDPC information bits of the 16K LDPC code is K_(ldpc), in order to form K_(ldpc) LDPC information bits, zero bits are padded.

In detail, when the number of BCH-encoded bits is N_(outer), the number of LDPC information bits of the 16K LDPC code is K_(ldpc), and N_(outer)<K_(ldpc), the zero padders 213 and 314 may pad the K_(ldpc)−N_(outer) zero bits and use the N_(outer) BCH-encoded bits as the remaining portion of the LDPC information bits to generate the LDPC information bits formed of K_(ldpc) bits. However, when N_(outer)=K_(ldpc), zero bits are not padded.

For this purpose, the zero padders 213 and 314 may divide the LDPC information bits into a plurality of bit groups.

For example, the zero padders 213 and 314 may divide the K_(ldpc) LDPC information bits (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹) into N_(info_group)(=K_(ldpc)/360) bit groups based on following Equation 13 or 14. That is, the zero padders 213 and 314 may divide the LDPC information bits into the plurality of bit groups so that the number of bits included in each bit group is 360.

$\begin{matrix} {Z_{i} = {{\left\{ {{{i_{k}❘j} = \left\lfloor \frac{k}{360} \right\rfloor},{0 \leq k < k_{ldpc}}} \right\}\mspace{14mu}{for}\mspace{14mu} 0} \leq j < N_{{info}\;\_\;{group}}}} & (13) \\ {Z_{j} = {{\left\{ {i_{k}❘{{360 \times j} \leq k < {360 \times \left( {j + 1} \right)}}} \right\}\mspace{14mu}{for}\mspace{14mu} 0} \leq j < N_{{info}\;\_\;{group}}}} & (14) \end{matrix}$

In above Equations 13 and 14, Z_(j) represents a j-th bit group.

Meanwhile, parameters N_(outer), K_(ldpc), and N_(info_group) for the zero padding for the L1-basic signaling and the L1-detail signaling may be defined as shown in following Table 7. In this case, the zero padders 213 and 314 may determine parameters for the zero padding according to a corresponding mode as shown in following Table 7.

TABLE 7 Signaimg FEC Type N_(outer) K_(idpc) N_(info)_group L1-Basic 358 3240  9 (all modes) L1-Detail Mode 1 568~2520 L1-Detail Mode 2 568~3240 L1-Detail Mode 3 568 - 6480 6480 18 L1-Detail Mode 4 L1-Detail Mode 5 L1-Detail Mode 6 L1-Detail Mode 7

Further, for 0≤j<N_(info_group), each bit group Z_(j) as shown in FIG. 16 may be formed of 360 bits.

In detail, FIG. 16 illustrates a data format after the L1-basic signaling and the L1-detail signaling each are LDPC-encoded. In FIG. 16, an LDPC FEC added to the K_(ldpc) LDPC information bits represents the LDPC parity bits generated by the LDPC encoding.

Referring to FIG. 16, the K_(ldpc) LDPC information bits are divided into the N_(info_group) bits groups and each bit group may be formed of 360 bits.

Meanwhile, when the number N_(outer)(=K_(sig)+M_(outer)) of BCH-encoded bits for the L1-basic signaling and the L1-detail signaling is less than the K_(ldpc), that is, N_(outer)(=K_(sig)+M_(outer))<K_(ldpc), for the LDPC encoding, the K_(ldpc) LDPC information bits may be filled with the N_(outer) BCH-encoded bits and the K_(ldpc)−N_(outer) zero-padded bits. In this case, the padded zero bits are not transmitted to the receiver 200.

Hereinafter, a shortening procedure performed by the zero padders 213 and 314 will be described in more detail.

The zero padders 213 and 314 may calculate the number of padded zero bits. That is, to fit the number of bits required for the LDPC encoding, the zero padders 213 and 314 may calculate the number of zero bits to be padded.

In detail, the zero padders 213 and 314 may calculate a difference between the number of LDPC information bits and the number of BCH-encoded bits as the number of padded zero bits. That is, for a given N_(outer), the zero padders 213 and 314 may calculate the number of padded zero bits as K_(ldpc)−N_(outer).

Further, the zero padders 213 and 314 may calculate the number of bit groups in which all the bits are padded. That is, the zero padders 213 and 314 may calculate the number of bit groups in which all bits within the bit group are padded by zero bits.

In detail, the zero padders 213 and 314 may calculate the number N_(pa)a of groups to which all bits are padded based on following Equation 15 or 16.

$\begin{matrix} {N_{pad} = \left\lfloor \frac{K_{ldpc} - N_{outer}}{360} \right\rfloor} & (15) \\ {N_{pad} = \left\lfloor \frac{\left( {K_{ldpc} - M_{outer}} \right) - K_{sig}}{360} \right\rfloor} & (16) \end{matrix}$

Next, the zero padders 213 and 314 may determine bit groups in which zero bits are padded among a plurality of bit groups based on a shortening pattern, and may pad zero bits to all bits within some of the determined bit groups and some bits within the remaining bit groups.

In this case, the shortening pattern of the padded bit group may be defined as shown in following Table 8. In this case, the zero padders 213 and 314 may determine the shortening pattern according to a corresponding mode as shown in following Table 8.

TABLE 8 Signaling FEC Type N_(info)_group π_(S)(j) (0 ≤ j < N_(info)_group) π_(S)(0) π_(S)(1) π_(S)(2) π_(S)(3) π_(S)(4) π_(S)(5) π_(S)(6) π_(S)(7) π_(S)(8) π_(S)(9) π_(S)(10) π_(S)(11) π_(S)(12) π_(S)(13) π_(S)(14) π_(S)(15) π_(S)(16) π_(S)(17) L1-Basic 9 4 1 5 2 8 6 0 7 3 (for all modes) — — — — — — — — — L1-Detail Mode 1 7 8 5 4 1 2 6 3 0 — — — — — — — — — L1-Detail Mode 2 6 1 7 8 0 2 4 3 5 — — — — — — — — — L1-Detail Mode 3 18 0 12 15 13 2 5 7 9 8 6 16 10 14 1 17 11 4 3 L1-Detail Mode 4 0 15 5 16 17 1 6 13 11 4 7 12 8 14 2 3 9 10 L1-Detail Mode 5 2 4 5 17 9 7 1 6 15 8 10 14 16 0 11 13 12 3 L1-Detail Mode 6 0 15 5 16 17 1 6 13 11 4 7 12 8 14 2 3 9 10 L1-Detail Mode 7 15  7 8 11 5 10 16 4 12 3 0 6 9 1 14 17 2 13

Here, π_(s)(j) is an index of a j-th padded bit group. That is, the π_(s)(j) represents a shortening pattern order of the j-th bit group. Further, N_(info_group) is the number of bit groups configuring the LDPC information bits.

In detail, the zero padders 213 and 314 may determine Z_(π) _(s) ₍₀₎, Z_(π) _(s) ₍₁₎, . . . , Z_(π) _(s) _((N) _(pad) ⁻¹⁾ as bit groups in which all bits within the bit group are padded by zero bits based on the shortening pattern, and pad zero bits to all bits of the bit groups. That is, the zero padders 213 and 314 may pad zero bits to all bits of a π_(s)(0)-th bit group, a π_(s)(1)-th bit group, . . . a π_(s)(N_(pad)−1)-th bit group among the plurality of bit groups based on the shortening pattern.

As such, when N_(pad) is not 0, the zero padders 213 and 314 may determine a list of the N_(pad) bit groups, that is, Z_(π) _(s) ₍₀₎, Z_(π) _(s) ₍₁₎, . . . , Z_(π) _(s) _((N) _(pad) ⁻¹⁾ based on above Table 8, and pad zero bits to all bits within the determined bit group.

However, when the N_(pad) is 0, the foregoing procedure may be omitted.

Meanwhile, since the number of all the padded zero bits is K_(ldpc)−N_(outer) and the number of zero bits padded to the N_(pad) bit groups is 360λN_(pad), the zero padders 213 and 314 may additionally pad zero bits to K_(ldpc)−N_(outer)−360×N_(pad) LDPC information bits.

In this case, the zero padders 213 and 314 may determine a bit group to which zero bits are additionally padded based on the shortening pattern, and may additionally pad zero bits from a head portion of the determined bit group.

In detail, the zero padders 213 and 314 may determine Z_(π) _(s) _((N) _(pad) ₎ as a bit group to which zero bits are additionally padded based on the shortening pattern, and may additionally pad zero bits to K_(ldpc)−N_(outer)−360×N_(pad) bits positioned at the head portion of Z_(π) _(s) _((N) _(pad) ₎. Therefore, K_(ldpc)−N_(outer)−360×N_(pad) zero bits may be padded from a first bit of the π_(s)(N_(pad))-th bit group.

As a result, for Z_(π) _(s) _((N) _(pad) ₎, zero bits may be additionally padded to the K_(ldpc)−N_(bch)−360×N_(pad) bits positioned at the head portion of the Z_(π) _(s) _((N) _(pad) ₎.

Meanwhile, the foregoing example describes that K_(ldpc)−N_(outer)−360×N_(pad) zero bits are padded from a first bit of Z_(π) _(s) _((N) _(pad) ₎, which is only one example. Therefore, the position at which zero bits are padded in Z_(π) _(s) _((N) _(pad) ₎ may be changed. For example, K_(ldpc)−N_(outer)−360×N_(pad) zero bits may be padded to a middle portion or a last portion of Z_(π) _(s) _((N) _(pad) ₎ or may also be padded at any position of Z_(π) _(s) _((N) _(pad) ₎.

Next, the zero padders 213 and 314 may map the BCH-encoded bits to the positions at which zero bits are not padded to configure the LDPC information bits.

Therefore, N_(outer) BCH-encoded bits are sequentially mapped to the bit positions at which zero bits are not padded in the K_(ldpc) LDPC information bits (i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹), and thus, K_(ldpc) LDPC information bits may be formed of N_(outer) BCH-encoded bits and K_(ldpc)−N_(outer) bits.

Meanwhile, the padded zero bits are not transmitted to the receiver 200. As such, a procedure of padding the zero bits or a procedure of padding the zero bits and then not transmitting the padded zero bits to the receiver 200 may be called shortening.

The LDPC encoders 214 and 315 perform LDPC encoding on the L1-basic signaling and the L1-detail signaling, respectively.

In detail, the LDPC encoders 214 and 315 may perform LDPC encoding on the LDPC information bits output from the zero padders 213 and 31 to generate LDPC parity bits, and output an LDPC codeword including the LDPC information bits and the LDPC parity bits to the parity permutators 215 and 316, respectively.

That is, K_(ldpc) bits output from the zero padder 213 may include K_(sig) L1-basic signaling bits, M_(outer) (=N_(outer)−K_(sig)) BCH parity check bits, and K_(ldpc)−N_(outer) padded zero bits, which may configure K_(ldpc) LDPC information bits i=(i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹) for the LDPC encoder 214.

Further, the K_(ldpc) bits output from the zero padder 314 may include the K_(sig) L1-detail signaling bits, the M_(outer) (=N_(outer)−K_(sig)) BCH parity check bits, and the (K_(ldpc)−N_(outer)) padded zero bits, which may configure the K_(ldpc) LDPC information bits i=(i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹) for the LDPC encoder 315.

In this case, the LDPC encoders 214 and 315 may systematically perform the LDPC encoding on the K_(ldpc) LDPC information bits to generate an LDPC codeword Λ=(c₀, c₁, . . . , c_(N) _(inner) ⁻¹)=(i₀, i₁, . . . , i_(K) _(ldpc) ⁻¹, p₀, p₁, . . . , p_(N) _(inner) _(−K) _(ldpc) ⁻¹) formed of N_(inner) bits.

Meanwhile, in the cases of the L1-basic modes and the L1-detail modes 1 and 2, the LDPC encoders 214 and 315 may encode the L1-basic signaling and the L1-detail signaling at a code rate of 3/15 to generate 16200 LDPC codeword bits. In this case, the LDPC encoders 214 and 315 may perform the LDPC encoding based on above Table 1.

Further, in the cases of the L1-detail modes 3, 4, 5 6, and 7, the LDPC encoder 315 may encode the L1-detail signaling at a code rate of 6/15 to generate the 16200 LDPC codeword bits. In this case, the LDPC encoder 315 may perform the LDPC encoding based on above Table 3.

Meanwhile, the code rate and the code length for the L1-basic signaling and the L1-detail signaling are as shown in above Table 4, and the number of LDPC information bits are as shown in above Table 7.

The parity permutators 215 and 316 perform parity permutation. That is, the parity permutators 215 and 316 may perform permutation only on the LDPC parity bits among the LDPC information bits and the LDPC parity bits.

In detail, the parity permutators 215 and 316 may perform the permutation only on the LDPC parity bits in the LDPC codewords output from the LDPC encoders 214 and 315, and output the parity permutated LDPC codewords to the repeaters 216 and 317, respectively. Meanwhile, the parity permutator 316 may output the parity permutated LDPC codeword to an additional parity generator 319. In this case, the additional parity generator 319 may use the parity permutated LDPC codeword output from the parity permutator 316 to generate additional parity bits.

For this purpose, the parity permutators 215 and 316 may include a parity interleaver (not illustrated) and a group-wise interleaver (not illustrated).

First, the parity interleaver may interleave only the LDPC parity bits among the LDPC information bits and the LDPC parity bits configuring the LDPC codeword. However, the parity interleaver may perform the parity interleaving only in the cases of the L1-detail modes 3, 4, 5, 6 and 7. That is, since the L1-basic modes and the L1-detail modes 1 and 2 include the parity interleaving as a portion of the LDPC encoding process, in the L1-basic modes and the L1-detail modes 1 and 2, the parity interleaver may not perform the parity interleaving.

Meanwhile, in the mode of performing the parity interleaving, the parity interleaver may interleave the LDPC parity bits based on following Equation 17.

u _(i) =c _(i) for 0≤i<K _(ldpc)(information bits are not interleaved.)

u _(K) _(ldpc) _(+360t+s) =c _(K) _(ldpc) _(+27s+t) for 0≤s<360, 0≤t<27  (17)

In detail, based on above Equation 17, the LDPC codeword (c₀, c₁, . . . , c_(N) _(inner) ⁻¹) is parity-interleaved by the parity interleaver and an output of the parity interleaver may be represented by U=(u₀, u₁, . . . , u_(N) _(inner) ⁻¹).

Meanwhile, since the L1-basic modes and the L1-detail modes 1 and 2 do not use the parity interleaver, an output U=(u₀, u₁, . . . , u_(N) _(inner) ⁻¹) of the parity interleaver may be represented as following Equation 18.

u _(i) =c _(i) for 0≤i<N _(inner)  (8)

Meanwhile, the group-wise interleaver may perform group-wise interleaving on the output of the parity interleaver.

Here, as described above, the output of the parity interleaver may be an LDPC codeword parity-interleaved by the parity interleaver or may be an LDPC codeword which is not parity-interleaved by the parity interleaver.

Therefore, when the parity interleaving is performed, the group-wise interleaver may perform the group-wise interleaving on the parity interleaved LDPC codeword, and when the parity interleaving is not performed, the group-wise interleaver may perform the group-wise interleaving on the LDPC codeword which is not parity-interleaved.

In detail, the group-wise interleaver may interleave the output of the parity interleaver in a bit group unit.

For this purpose, the group-wise interleaver may divide an LDPC codeword output from the parity interleaver into a plurality of bit groups. As a result, the LDPC parity bits output from the parity interleaver may be divided into a plurality of bit groups.

In detail, the group-wise interleaver may divide the LDPC-encoded bits (u₀, u₁, . . . , u_(N) _(inner) ⁻¹) output from the parity interleaver into N_(group)(=N_(inner)/360) bit groups based on following Equation 19.

X _(j) ={u _(k)|360×j≤k<360×(j+1),0≤k<N _(inner)} for 0≤j<N _(group)  (19)

In above Equation 19, X_(j) represents a j-th bit group.

FIG. 17 illustrates an example of dividing the LDPC codeword output from the parity interleaver into a plurality of bit groups.

Referring to FIG. 17, the LDPC codeword is divided into the N_(group)(=N_(inner)/360) bit groups, and each bit group X_(j) for 0≤j<N_(group) is formed of 360 bits.

As a result, the LDPC information bits formed of K_(ldpc) bits may be divided into K_(ldpc)/360 bit groups and the LDPC parity bits formed of N_(inner)−K_(ldpc) bits may be divided into N_(inner)−K_(ldpc)/360 bit groups.

Further, the group-wise interleaver performs the group-wise interleaving on the LDPC codeword output from the parity interleaver.

In this case, the group-wise interleaver does not perform interleaving on the LDPC information bits, and may perform the interleaving only on the LDPC parity bits to change the order of a plurality of bit groups configuring the LDPC parity bits.

As a result, the LDPC information bits among the LDPC bits may not be interleaved by the group-wise interleaver but the LDPC parity bits among the LDPC bits may be interleaved by the group-wise interleaver. In this case, the LDPC parity bits may be interleaved in a group unit.

In detail, the group-wise interleaver may perform the group-wise interleaving on the LDPC codeword output from the parity interleaver based on following Equation 20.

Y _(j) =X _(j),0≤j<K _(ldpc)/360

Y _(j) =X _(πp(j)) ,K _(ldpc)/360≤j<N _(group)  (20)

Here, X_(j) represents a j-th bit group among the plurality of bit groups configuring the LDPC codeword, that is, the j-th bit group which is not group-wise interleaved, and Y_(j) represents the group-wise interleaved j-th bit group. Further, π_(p)(j) represents a permutation order for the group-wise interleaving.

Meanwhile, the permutation order may be defined based on following Table 9 and Table 10. Here, Table 9 shows a group-wise interleaving pattern of a parity portion in the L1-basic modes and the L1-detail modes 1 and 2, and Table 10 shows a group-wise interleaving pattern of a parity portion for the L1-detail modes 3, 4, 5, 6 and 7.

In this case, the group-wise interleaver may determine the group-wise interleaving pattern according to a corresponding mode shown in following Tables 9 and 10.

TABLE 9 Signaling Order of group-wise interleaving FEC Type N_(group) π_(p)(j) (9 ≤ j < 45) π_(p)(9) π_(p)(10) π_(p)(11) π_(p)(12) π_(p)(13) π_(p)(14) π_(p)(15) π_(p)(16) π_(p)(17) π_(p)(18) π_(p)(19) π_(p)(20) π_(p)(21) π_(p)(22) π_(p)(23) π_(p)(24) π_(p)(25) π_(p)(26) π_(p)(27) π_(p)(28) π_(p)(29) π_(p)(30) π_(p)(31) π_(p)(32) π_(p)(33) π_(p)(34) π_(p)(35) π_(p)(36) π_(p)(37) π_(p)(38) π_(p)(39) π_(p)(40) π_(p)(41) π_(p)(42) π_(p)(43) π_(p)(44) L1-Basic 45 20 23 25 32 38 41 18 9 10 11 31 24 (all modes) 14 15 26 40 33 19 28 34 16 39 27 30 21 44 43 35 42 36 12 13 29 22 37 17 L1-Detail 16 22 27 30 37 44 20 23 25 32 38 41 Mode 1 9 10 17 18 21 33 35 14 28 12 15 19 11 24 29 34 36 13 40 43 31 26 39 42 L1-Detail 9 31 23 10 11 25 43 29 36 16 27 34 Mode 2 26 18 37 15 13 17 35 21 20 24 44 12 22 40 19 32 38 41 30 33 14 28 39 42

TABLE 10 Sig- nal- ing FEC Order of group-wise interleaving Type N_(group) π_(p)(j) (18 ≤ j < 45) π_(p)(18) π_(p)(19) π_(p)(20) π_(p)(21) π_(p)(22) π_(p)(23) π_(p)(24) π_(p)(25) π_(p)(26) π_(p)(27) π_(p)(28) π_(p)(29) π_(p)(30) π_(p)(31) π_(p)(32) π_(p)(33) π_(p)(34) π_(p)(35) π_(p)(36) π_(p)(37) π_(p)(38) π_(p)(39) π_(p)(40) π_(p)(41) π_(p)(42) π_(p)(43) π_(p)(44) L1- 45 19 37 30 42 23 44 27 40 21 34 25 32 29 24 De- 26 35 39 20 18 43 31 36 38 22 33 28 41 tail Mode 3 L1- 20 35 42 39 26 23 30 18 28 37 32 27 44 43 De- 41 40 38 36 34 33 31 29 25 24 22 21 19 tail Mode 4 L1- 19 37 33 26 40 43 22 29 24 35 44 31 27 20 De- 21 39 25 42 34 18 32 38 23 30 28 36 41 tail Mode 5 L1- 20 35 42 39 26 23 30 18 28 37 32 27 44 43 De- 41 40 38 36 34 33 31 29 25 24 22 21 19 tail Mode 6 L1- 44 23 29 33 24 28 21 27 42 18 22 31 32 37 De- 43 30 25 35 20 34 39 36 19 41 40 26 38 tail Mode 7

Hereinafter, for the group-wise interleaving pattern in the L1-detail mode 2 as an example, an operation of the group-wise interleaver will be described.

In the L1-detail mode 2, the LDPC encoder 315 performs LDPC encoding on 3240 LDPC information bits at a code rate of 3/15 to generate 12960 LDPC parity bits. In this case, an LDPC codeword may be formed of 16200 bits.

Meanwhile, each bit group is formed of 360 bits, and as a result the LDPC codeword formed of 16200 bits is divided into 45 bit groups.

Here, since the number of the LDPC information bits is 3240 and the number of the LDPC parity bits is 12960, a 0-th bit group to an 8-th bit group correspond to the LDPC information bits and a 9-th bit group to a 44-th bit group correspond to the LDPC parity bits.

In this case, the group-wise interleaver does not perform interleaving on the bit groups configuring the LDPC information bits, that is, a 0-th bit group to a 8-th bit group based on above Equation 20 and Table 9, but may interleave the bit groups configuring the LDPC parity bits, that is, a 9-th bit group to a 44-th bit group in a group unit to change an order of the 9-th bit group to the 44-th bit group.

In detail, in the L1-detail mode 2 in above Table 9, above Equation 20 may be represented like Y₀=X₀, Y₁=X₁, . . . , Y₇=X₇, Y₈=X₈, Y₉=X_(πp(9))=X₉, Y₁₀=X_(πp(10))=X₃₁, Y₁₁=X_(πp(11))=X₂₃, . . . , Y₄₂=X_(πp(42))=X₂₉, Y₄₃=X_(πp(43))=X₃₉, Y₄₄=X_(πp(44))=X₄₂.

Therefore, the group-wise interleaver does not change an order of the 0-th bit group to the 8-th bit group including the LDPC information bits but may change an order of the 9-th bit group to the 44-th bit group including the LDPC parity bits.

In detail, the group-wise interleaver may change the order of the bit groups from the 9-th bit group to the 44-th bit group so that the 9-th bit group is positioned at the 9-th position, the 31-th bit group is positioned at the 10-th position, the 23-th bit group is positioned at the 11-th position, . . . , the 28-th bit group is positioned at the 42-th position, the 39-th bit group is positioned at the 43-th position, the 42-th bit group is positioned at the 44-th position.

Meanwhile, as described below, since the puncturers 217 and 318 perform puncturing from the last parity bit, the parity bit groups may be arranged in an inverse order of the puncturing pattern by the parity permutation. That is, the first bit group to be punctured is positioned at the last bit group.

Meanwhile, the foregoing example describes that only the parity bits are interleaved, which is only one example. That is, the parity permutators 215 and 316 may also interleave the LDPC information bits. In this case, the parity permutators 215 and 316 may interleave the LDPC information bits with identity and output the LDPC information bits having the same order before the interleaving so that the order of the LDPC information bits is not changed.

The repeaters 216 and 317 may repeat at least some bits of the parity permutated LDPC codeword at a position subsequent to the LDPC information bits, and output the repeated LDPC codeword, that is, the LDPC codeword bits including the repetition bits, to the puncturers 217 and 318. Meanwhile, the repeater 317 may also output the repeated LDPC codeword to the additional parity generator 319. In this case, the additional parity generator 319 may use the repeated LDPC codeword to generate the additional parity bits.

In detail, the repeaters 216 and 317 may repeat a predetermined number of LDPC parity bits after the LDPC information bits. That is, the repeaters 216 and 317 may add the predetermined number of repeated LDPC parity bits after the LDPC information bits. Therefore, the repeated LDPC parity bits are positioned between the LDPC information bits and the LDPC parity bits within the LDPC codeword.

Therefore, since the predetermined number of bits within the LDPC codeword after the repetition may be repeated and additionally transmitted to the receiver 200, the foregoing operation may be referred to as repetition.

Meanwhile, the term “adding” represents disposing the repetition bits between the LDPC information bits and the LDPC parity bits so that the bits are repeated.

The repetition may be performed only on the L1-basic mode 1 and the L1-detail mode 1, and may not be performed on the other modes. In this case, the repeaters 216 and 317 do not perform the repetition, and may output the parity permutated LDPC codeword to the puncturers 217 and 318.

Hereinafter, a method for performing repetition will be described in more detail.

The repeaters 216 and 317 may calculate a number N_(repeat) of bits additionally transmitted per an LDPC codeword based on following Equation 21.

N _(repeat)=2×└C×N _(outer) ┘+D  (21)

In above Equation 21, C has a fixed number and D may be an even integer. Referring to above Equation 21, it may be appreciated that the number of bits to be repeated may be calculated by multiplying C by a given N_(outer) and adding D thereto.

Meanwhile, the parameters C and D for the repetition may be selected based on following Table 11. That is, the repeaters 216 and 317 may determine the C and D based on a corresponding mode as shown in following Table 11.

TABLE 11 N_(ldpc)_parity N_(outer) K_(sig) K_(ldpc) C D (=N_(inner) − K_(ldpc)) η_(MOD) L1-Basic Mode 1 368 200 3240 0 3672 12960 2 L1-Detail Mode 1 568~2520 400~2352 3240 61/16 ~508 12960 2

Further, the repeaters 216 and 317 may repeat N_(repeat) LDPC parity bits.

In detail, when N_(repeat)<N_(ldpc_parity), the repeaters 216 and 317 may add first N_(repeat) bits of the parity permutated LDPC parity bits to the LDPC information bits as illustrated in FIG. 18. That is, the repeaters 216 and 317 may add a first LDPC parity bit among the parity permutated LDPC parity bits as an N_(repeat)-th LDPC parity bit after the LDPC information bits.

Meanwhile, when N_(repeat)>N_(ldpc_parity), the repeaters 216 and 317 may add the parity permutated N_(ldpc_parity) LDPC parity bits to the LDPC information bits as illustrated in FIG. 19, and may additionally add an N_(repeat)−N_(ldpc_parity) number of the parity permutated LDPC parity bits to the N_(ldpc_parity) LDPC parity bits which are first added. That is, the repeaters 216 and 317 may add all the parity permutated LDPC parity bits after the LDPC information bits and additionally add the first LDPC parity bit to the N_(repeat)−N_(ldpc_parity)-th LDPC parity bit among the parity permutated LDPC parity bits after the LDPC parity bits which are first added.

Therefore, in the L1-basic mode 1 and the L1-detail mode 1, the additional N_(repeat) bits may be selected within the LDPC codeword and transmitted.

The puncturers 217 and 318 may puncture some of the LDPC parity bits included in the LDPC codeword output from the repeaters 216 and 317, and output a punctured LDPC codeword (that is, the remaining LDPC codeword bits other than the punctured bits and also referred to as an LDPC codeword after puncturing) to the zero removers 218 and 321. Further, the puncturer 318 may provide information (for example, the number and positions of punctured bits, etc.) about the punctured LDPC parity bits to the additional parity generator 319. In this case, the additional parity generator 319 may generate additional parity bits based thereon.

As a result, after going through the parity permutation, some LDPC parity bits may be punctured.

In this case, the punctured LDPC parity bits are not transmitted in a frame in which L1 signaling bits are transmitted. In detail, the punctured LDPC parity bits are not transmitted in a current frame in which the L1-signaling bits are transmitted, and in some cases, the punctured LDPC parity bits may be transmitted in a frame before the current frame, which will be described with reference to the additional parity generator 319.

For this purpose, the puncturers 217 and 318 may determine the number of LDPC parity bits to be punctured per LDPC codeword and a size of one coded block.

In detail, the puncturers 217 and 318 may calculate a temporary number N_(punc_temp) of LDPC parity bits to be punctured based on following Equation 22. That is, for a given N_(outer), the puncturers 217 and 318 may calculate the temporary number N_(punc_temp) of LDPC parity bits to be punctured based on following Equation 22

N _(punc_temp) =└A×(K _(ldpc) −N _(outer))┘+B  (22)

Referring to above Equation 22, the temporary size of bits to be punctured may be calculated by adding a constant integer B to an integer obtained from a result of multiplying a shortening length (that is, K_(ldpc)−N_(outer)) by a preset constant A value. In the present exemplary embodiment, it is apparent that the constant A value is set at a ratio of the number of bits to be punctured to the number of bits to be shortened but may be variously set according to requirements of a system.

Here, the B value is a value which represents a length of bits to be punctured even when the shortening length is 0, and thus, represents a minimum length that the punctured bits can have. Further, the A and B values serve to adjust an actually transmitted code rate. That is, to prepare for a case in which the length of information bits, that is, the length of the L1 signaling is short or a case in which the length of the L1 signaling is long, the A and B values serve to adjust the actually transmitted code rate to be reduced.

Meanwhile, the above K_(ldpc), A and B are listed in following Table 12 which shows parameters for puncturing. Therefore, the puncturers 217 and 318 may determine the parameters for puncturing according to a corresponding mode as shown in following Table 12.

TABLE 12 Signaling FEC Type N_(outer) K_(ldpc) A B N_(ldpc)_parity η_(MOD) L1-Basic Mode 1 368 3240 0 9360 12960 2 Mode 2 11460 2 Mode 3 12360 2 Mode 4 12292 4 Mode 5 12350 6 Mode 6 12432 8 Mode 7 12776 8 L1-Detail Mode 1 568~2520 7/2 0 2 Mode 2 568~3240 2 6036 2 Mode 3 568~6480 6480 11/16 4653 9720 2 Mode 4 29/32 3200 4 Mode 5 3/4 4284 6 Mode 6 11/16 4900 8 Mode 7  49/256 8246 8

Meanwhile, the puncturers 217 and 318 may calculate a temporary size N_(FEC_temp) of one coded block as shown in following Equation 23. Here, the number N_(ldpc_parity) of LDPC parity bits according to a corresponding mode is shown as above Table 12.

N _(FEC_temp) =N _(outer) +N _(ldpc_parity) −N _(punc_temp)  (23)

Further, the puncturers 217 and 318 may calculate a size N_(FEC) of one coded block as shown in following Equation 24.

$\begin{matrix} {N_{FEC} = {\left\lceil \frac{N_{{FEC}\;\_\;{temp}}}{\eta_{MOD}} \right\rceil \times \eta_{MOD}}} & (24) \end{matrix}$

In above Equation 24, η_(MOD) is a modulation order. For example, when the L1-basic signaling and the L1-detail signaling are modulated by QPSK, 16-QAM, 64-QAM or 256-QAM according to a corresponding mode, η_(MOD) may be 2, 4, 6 and 8 as shown in above Table 12. Meanwhile, according to above Equation 24, the N_(FE)c may be an integer multiple of the modulation order.

Further, the puncturers 217 and 318 may calculate the number N_(punc) of LDPC parity bits to be punctured based on following Equation 25.

N _(punc) =N _(punc_temp)−(N _(FEC) −N _(FEC_temp))  (25)

Here, N_(punc) is 0 or a positive integer. Further, N_(FEC) is the number of bits of an information block which are obtained by subtracting N_(punc) bits to be punctured from N_(outer)+N_(ldpc_parity) bits obtained by performing the BCH encoding and the LDPC encoding on K_(sig) information bits. That is, N_(FEC) is the number of bits other than the repetition bits among the actually transmitted bits, and may be called the number of shortened and punctured LDPC codeword bits.

Referring to the foregoing process, the puncturers 217 and 318 multiplies A by the number of padded zero bits, that is, a shortening length and adding B to a result to calculate the temporary number N_(punc_temp) of LDPC parity bits to be punctured.

Further, the puncturers 217 and 318 calculate the temporary number N_(FEC_temp) of LDPC codeword bits to constitute the LDPC codeword after puncturing and shortening based on the N_(punc_temp).

In detail, the LDPC information bits are LDPC-encoded, and the LDPC parity bits generated by the LDPC encoding are added to the LDPC information bits to configure the LDPC codeword. Here, the LDPC information bits include the BCH-encoded bits in which the L1-basic signaling and the L1-detail signaling are BCH encoded, and in some cases, may further include padded zero bits.

In this case, since the padded zero bits are LDPC-encoded, and then, are not transmitted to the receiver 200, the shortened LDPC codeword, that is, the LDPC codeword (that is, shortened LDPC codeword) except the padded zero bits may be formed of the BCH-encoded bits and LDPC parity bits.

Therefore, the puncturers 217 and 318 subtract the temporary number of LDPC parity bits to be punctured from a sum of the number of BCH-encoded bits and the number of LDPC parity bits to calculate the N_(FEC_temp).

Meanwhile, the punctured and shortened LDPC codeword (that is, LDPC codeword bits remaining after puncturing and shortening) are mapped to constellation symbols by various modulation schemes such as QPSK, 16-QAM, 64-QAM or 256-QAM according to a corresponding mode, and the constellation symbols may be transmitted to the receiver 200 through a frame.

Therefore, the puncturers 217 and 318 determine the number N_(FEC) of LDPC codeword bits to constitute the LDPC codeword after puncturing and shortening based on N_(FEC_temp), N_(FEC) being an integer multiple of the modulation order, and determine the number N_(punc) of bits which need to be punctured based on LDPC codeword bits after shortening to obtain the N_(FEC).

Meanwhile, when zero bits are not padded, an LDPC codeword may be formed of BCH-encoded bits and LDPC parity bits, and the shortening may be omitted.

Further, in the L1-basic mode 1 and the L1-detail mode 1, repetition is performed, and thus, the number of shortened and punctured LDPC codeword bits is equal to N_(FEC)+N_(repeat).

Meanwhile, the puncturers 217 and 318 may puncture the LDPC parity bits as many as the calculated number.

In this case, the puncturers 217 and 318 may puncture the last N_(punc) bits of all the LDPC codewords. That is, the puncturers 217 and 318 may puncture the N_(punc) bits from the last LDPC parity bits.

In detail, when the repetition is not performed, the parity permutated LDPC codeword includes only LDPC parity bits generated by the LDPC encoding.

In this case, the puncturers 217 and 318 may puncture the last N_(punc) bits of all the parity permutated LDPC codewords. Therefore, the N_(punc) bits from the last LDPC parity bits among the LDPC parity bits generated by the LDPC encoding may be punctured.

Meanwhile, when the repetition is performed, the parity permutated and repeated LDPC codeword includes the repeated LDPC parity bits and the LDPC parity bits generated by the LDPC encoding.

In this case, the puncturers 217 and 318 may puncture the last N_(punc) bits of all the parity permutated and repeated LDPC codewords, respectively, as illustrated in FIGS. 20 and 21.

In detail, the repeated LDPC parity bits are positioned between the LDPC information bits and the LDPC parity bits generated by the LDPC encoding, and thus, the puncturers 217 and 318 may puncture the N_(punc) bits from the last LDPC parity bits among the LDPC parity bits generated by the LDPC encoding, respectively.

As such, the puncturers 217 and 318 may puncture the N_(punc) bits from the last LDPC parity bits, respectively.

Meanwhile, N_(punc) is 0 or a positive integer and the repetition may be applied only to the L1-basic mode 1 and the L1-detail mode 1.

The foregoing example describes that the repetition is performed, and then, the puncturing is performed, which is only one example. In some cases, after the puncturing is performed, the repetition may be performed.

The additional parity generator 319 may select bits from the LDPC parity bits to generate additional parity (AP) bits.

In this case, the additional parity bits may be selected from the LDPC parity bits generated based on the L1-detail signaling transmitted in a current frame, and transmitted to the receiver 200 through a frame before the current frame, that is, a previous frame.

In detail, the L1-detail signaling is LDPC-encoded, and the LDPC parity bits generated by the LDPC encoding are added to the L1-detail signaling to configure an LDPC codeword.

Further, puncturing and shortening are performed on the LDPC codeword, and the punctured and shortened LDPC codeword may be mapped to a frame to be transmitted to the receiver 200. Here, when the repetition is performed according to a corresponding mode, the punctured and shortened LDPC codeword may include the repeated LDPC parity bits.

In this case, the L1-detail signaling corresponding to each frame may be transmitted to the receiver 200 through each frame, along with the LDPC parity bits. For example, the punctured and shortened LDPC codeword including the L1-detail signaling corresponding to an (i−1)-th frame may be mapped to the (i−1)-th frame to be transmitted to the receiver 200, and the punctured and shortened LDPC codeword including the L1-detail signaling corresponding to the i-th frame may be mapped to the i-th frame to be transmitted to the receiver 200.

Meanwhile, the additional parity generator 319 may select at least some of the LDPC parity bits generated based on the L1-detail signaling transmitted in the i-th frame to generate the additional parity bits.

In detail, some of the LDPC parity bits generated by performing the LDPC encoding on the L1-detail signaling are punctured, and then, are not transmitted to the receiver 200. In this case, the additional parity generator 319 may select at least some of the punctured LDPC parity bits among the LDPC parity bits generated by performing the LDPC encoding on the L1-detail signaling transmitted in the i-th frame, thereby generating the additional parity bits.

Further, the additional parity generator 319 may select at least some of the LDPC parity bits to be transmitted to the receiver 200 through the i-th frame to generate the additional parity bits.

In detail, the LDPC parity bits included in the punctured and shortened LDPC codeword to be mapped to the i-th frame may be configured of only the LDPC parity bits generated by the LDPC encoding according to a corresponding mode or the LDPC parity bits generated by the LDPC encoding and the repeated LDPC parity bits.

In this case, the additional parity generator 319 may select at least some of the LDPC parity bits included in the punctured and shortened LDPC codeword to be mapped to the i-th frame to generate the additional parity bits.

Meanwhile, the additional parity bits may be transmitted to the receiver 200 through the frame before the i-th frame, that is, the (i−1)-th frame.

That is, the transmitter 100 may not only transmit the punctured and shortened LDPC codeword including the L1-detail signaling corresponding to the (i−1)-th frame but also transmit the additional parity bits generated based on the L1-detail signaling transmitted in the i-th frame to the receiver 200 through the (i−1)-th frame.

In this case, the frame in which the additional parity bits are transmitted may be temporally the most previous frame among the frames before the current frame.

For example, the additional parity bits have the same bootstrap major/minor version as the current frame among the frames before the current frame, and may be transmitted in temporally the most previous frame.

Meanwhile, in some cases, the additional parity generator 319 may not generate the additional parity bits.

In this case, the transmitter 100 may transmit information about whether additional parity bits for an L1-detail signaling of a next frame are transmitted through the current frame to the receiver 200 using an L1-basic signaling transmitted through the current frame.

For example, the use of the additional parity bits for the L1-detail signaling of the next frame having the same bootstrap major/minor version as the current frame may be signaled through a field L1B_L1_Detail_additional_parity_mode of the L1-basic parameter of the current frame. In detail, when the L1B_L1_Detail_additional_parity_mode in the L1-basic parameter of the current frame is set to be ‘00’, additional parity bits for the L1-detail signaling of the next frame are not transmitted in the current frame.

As such, to additionally increase robustness of the L1-detail signaling, the additional parity bits may be transmitted in the frame before the current frame in which the L1-detail signaling of the current frame is transmitted.

FIG. 22 illustrates an example in which the additional parity bits for the L1-detail signaling of the i-th frame are transmitted in a preamble of the (i−1) th frame.

FIG. 22 illustrates that the L1-detail signaling transmitted through the i-th frame is segmented into M blocks by segmentation and each of the segmented blocks is FEC encoded.

Therefore, M number of LDPC codewords, that is, an LDPC codeword including LDPC information bits L1-D(i)_1 and parity bits parity for L1-D(i)_1 therefor, . . . , and an LDPC codeword including LDPC information bits L1-D(i)_M and parity bits parity for L1-D(i)_M therefor are mapped to the i-th frame to be transmitted to the receiver 200.

In this case, the additional parity bits generated based on the L1-detail signaling transmitted in the i-th frame may be transmitted to the receiver 200 through the (i−1)-th frame.

In detail, the additional parity bits, that is, AP for L1-D(i)_1, . . . AP for L1-D(i)_M generated based on the L1-detail signaling transmitted in the i-th frame may be mapped to the preamble of the (i−1)-th frame to be transmitted to the receiver 200. As a result of using the additional parity bits, a diversity gain for the L1 signaling may be obtained.

Hereinafter, a method for generating additional parity bits will be described in detail.

The additional parity generator 319 calculates a temporary number N_(AP_temp) of additional parity bits based on following Equation 26.

$\begin{matrix} {{N_{{AP}\;\_\;{temp}} = {\min\begin{Bmatrix} {{0.5 \times K \times \left( {N_{outer} + N_{{ldpc}\;\_\;{parity}} - N_{punc} + N_{repeat}} \right)},} \\ \left( {N_{{ldpc}\;\_\;{parity}} + N_{punc} + N_{repeat}} \right) \end{Bmatrix}}},{K = 0},1,2} & (26) \end{matrix}$

In above Equation 26,

${\min\left( {a,b} \right)} = \left\{ {\begin{matrix} {a,{{{if}\mspace{14mu} a} \leq b}} \\ {b,{{{if}\mspace{14mu} b} < a}} \end{matrix}.} \right.$

Further, K represents a ratio of the additional parity bits to a half of a total number of bits of a transmitted coded L1-detail signaling block (that is, bits configuring the L1-detail signaling block repeated, punctured, and have the zero bits removed (that is, shortened)).

In this case, K corresponds to an L1B_L1_Detail_additional_parity_mode field of the L1-basic signaling. Here, a value of the L1B_L1_Detail_additional_parity_mode associated with the L1-detail signaling of the i-th frame (that is, frame (#i)) may be transmitted in the (i−1)-th frame (that is, frame (#i−1)).

Meanwhile, as described above, when L1 detail modes are 2, 3, 4, 5, 6 and 7, since repetition is not performed, in above Equation 26, N_(repeat) is 0.

Further, the additional parity generator 319 calculates the number N_(AP) of additional parity bits based on following Equation 27. Therefore, the number N_(AP) of additional parity bits may be a multiple of a modulation order.

$\begin{matrix} {N_{AP} = {\left\lfloor \frac{N_{{AP}\;\_\;{temp}}}{\eta_{MOD}} \right\rfloor \times \eta_{MOD}}} & (27) \end{matrix}$

Here, └X┘ is a maximum integer which is not greater than x. Here, η_(MOD) is the modulation order. For example, when the L1-detail signaling is modulated by QPSK, 16-QAM, 64-QAM or 256-QAM according to a corresponding mode, the η_(MOD) may be 2, 4, 6 or 8.

As such, the number of additional parity bits may be determined based on the total number of bits transmitted in the current frame.

Next, the additional parity generator 319 may select bits as many as the number of bits calculated in the LDPC parity bits to generate the additional parity bits.

In detail, when the number of punctured LDPC parity bits is equal to or greater than the number of additional parity bits, the additional parity generator 319 may select bits as many as the calculated number from the first LDPC parity bit among the punctured LDPC parity bits to generate the additional parity bits.

Meanwhile, when the number of punctured LDPC parity bits is less than the number of additional parity bits, the additional parity generator 319 may first select all the punctured LDPC parity bits, and additionally select bits as many as the number obtained by subtracting the number of punctured LDPC parity bits from the number of additional parity bits calculated, from the first LDPC parity bit among the LDPC parity bits included in the LDPC codeword, to generate the additional parity bits.

In detail, when repetition is not performed, LDPC parity bits included in a repeated LDPC codeword are the LDPC parity bits generated by the LDPC encoding.

In this case, the additional parity generator 319 may first select all the punctured LDPC parity bits and additionally select bits as many as the number obtained by subtracting the number of punctured LDPC parity bits from the number of additional parity bits calculated, from the first LDPC parity bit among the LDPC parity bits generated by the LDPC encoding, to generate the additional parity bits.

Here, the LDPC parity bits generated by the LDPC encoding are divided into non-punctured LDPC parity bits and punctured LDPC parity bits. As a result, when the bits are selected from the first bit among the LDPC parity bits generated by the LDPC encoding, they may be selected in an order of the non-punctured LDPC parity bits and the punctured LDPC parity bits.

Meanwhile, when the repetition is performed, the LDPC parity bits included in the repeated LDPC codeword are the repeated LDPC parity bits and the LDPC parity bits generated by the encoding. Here, the repeated LDPC parity bits are positioned between the LDPC information bits and the LDPC parity bits generated by the LDPC encoding.

In this case, the additional parity generator 319 may first select all the punctured LDPC parity bits and additionally select bits as many as the number obtained by subtracting the number of punctured LDPC parity bits from the number of additional parity bits calculated, from the first LDPC parity bit among the repeated LDPC parity bits to generate the additional parity bits.

Here, when the bits are selected from the first bit among the repeated LDPC parity bits, they may be selected in an order of the repetition bits and the LDPC parity bits generated by the LDPC encoding. Further, the bits may be selected in an order of the non-punctured LDPC parity bits and the punctured LDPC parity bits, within the LDPC parity bits generated by the LDPC encoding.

Hereinafter, methods for generating additional parity bits according to exemplary embodiments will be described in more detail with reference to FIGS. 23 to 25.

FIGS. 23 to 25 are diagrams for describing the methods for generating additional parity bits when repetition is performed, according to the exemplary embodiments. In this case, a repeated LDPC codeword V=(v0, v1, . . . , v_(N) _(inner) _(+N) _(repeat) ⁻¹) may be represented as illustrated in FIG. 23.

First, when N_(AP)≤N_(punc), as illustrated in FIG. 24, the additional parity generator 319 may select N_(AP) bits from the first LDPC parity bit among punctured LDPC parity bits to generate the additional parity bits.

Therefore, for the additional parity bits, the punctured LDPC parity bits (v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) , v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) ₊₁, . . . , v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) _(−N) _(AP) ⁻¹) may be selected. That is, the additional parity generator 319 may select the N_(AP) bits from the first bit among the punctured LDPC parity bits to generate the additional parity bits.

Meanwhile, when N_(AP)>N_(punc), as illustrated in FIG. 25, the additional parity generator 319 selects all the punctured LDPC parity bits.

Therefore, for the additional parity bits, all the punctured LDPC parity bits (v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) , v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) ₊₁, v_(N) _(repeat) _(+N) _(inner) ⁻¹) may be selected.

Further, the additional parity generator 319 may additionally select first N_(AP)−N_(punc) bits from the LDPC parity bits including the repeated LDPC parity bits and the LDPC parity bits generated by the LDPC encoding.

That is, since the repeated LDPC parity bits and the LDPC parity bits generated by the LDPC encoding are sequentially arranged, the additional parity generator 319 may additionally select the N_(AP)−N_(punc) parity bits from the first LDPC parity bit among the repeated LDPC parity bits.

Therefore, for the additional parity bits, the LDPC parity bits (v_(K) _(ldpc) , v_(K) _(ldpc) ₊₁, . . . , v_(K) _(ldpc) _(+N) _(AP) _(−N) _(punc) ⁻¹) may be additionally selected.

In this case, the additional parity generator 319 may add the additionally selected bits to the previously selected bits to generate the additional parity bits. That is, as illustrated in FIG. 25, the additional parity generator 319 may add the additionally selected LDPC parity bits to the punctured LDPC parity bits to generate the additional parity bits.

As a result, for the additional parity bits, (v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) , v_(N) _(repeat) _(+N) _(inner) _(−N) _(punc) ₊₁, . . . , v_(N) _(repeat) _(+N) _(inner) ⁻¹, v_(K) _(ldpc) , v_(K) _(ldpc) ₊₁, . . . , v_(K) _(ldpc) _(+N) _(AP) _(−N) _(punc) ⁻¹) may be selected.

As such, when the number of punctured bits is equal to or greater than the number of additional parity bits, the additional parity bits may be generated by selecting bits among the punctured bits based on the puncturing order. On the other hand, in other cases, the additional parity bits may be generated by selecting all the punctured bits and the N_(AP)-N_(punc) parity bits.

Meanwhile, since N_(repeat)=0 when repetition is not performed, the method for generating additional parity bits when the repetition is not performed is the same as the case in which N_(repeat)=0 in FIGS. 23 to 25.

The additional parity bits may be bit-interleaved, and may be mapped to the constellation. In this case, the constellation for the additional parity bits may be generated by the same method as the constellation for the L1-detail signaling bits transmitted in the current frame, in which the L1-detail signaling bits are repeated, punctured, and have the zero bits removed. Further, as illustrated in FIG. 22, after being mapped to the constellation, the additional parity bits may be added after the L1-detail signaling block in the frame before the current frame in which the L1-detail signaling of the current frame is transmitted.

The additional parity generator 319 may output the additional parity bits to a bit demultiplexer 323.

Meanwhile, as described above in reference to Tables 9 and 10, the group-wise interleaving pattern defining the permutation order may have two patterns: a first pattern and a second pattern.

In detail, since the B value of above Equation 22 represents the minimum length of the LDPC parity bits to be punctured, the predetermined number of bits may be always punctured depending on the B value regardless of the length of the input signaling. For example, in the L1-detail mode 2, since B=6036 and the bit group is formed of 360 bits, even when the shortening length is 0, at least └6036/360┘=16 bit groups are always punctured.

In this case, since the puncturing is performed from the last LDPC parity bit, the predetermined number of bit groups from a last bit group among the plurality of bit groups configuring the group-wise interleaved LDPC parity bits may be always punctured regardless of the shortening length.

For example, in the L1-detail mode 2, the last 16 bit groups among 36 bit groups configuring the group-wise interleaved LDPC parity bits may be always punctured.

As a result, some of the group-wise interleaving patterns defining the permutation order represent bit groups always to punctured, and therefore, the group-wise interleaving pattern may be divided into two patterns. In detail, a pattern defining the remaining bit groups other than the bit groups always to be punctured in the group-wise interleaving pattern is referred to as the first pattern, and the pattern defining the bit groups always to be punctured is referred to as the second pattern.

For example, in the L1-detail mode 2, since the group-wise interleaving pattern is defined as above Table 9, a pattern representing indexes of bit groups which are not group-wise interleaved and positioned in a 9-th bit group to a 28-th bit group after group-wise interleaving, that is, Y₉=X_(πp(9))=X₉, Y₁₀=X_(πp(10))>=X₃₁, Y₁₁=X_(πp(11))>=X₂₃, . . . , Y₂₆=X_(πp(26))=X₁₇, Y₂₇=X_(πp(27))=X₃₅, Y₂₈=X_(πp(28))=X₂₁ may be the first pattern, and a pattern representing indexes of bit groups which are not group-wise interleaved and positioned in a 29-th bit group to a 44-th bit group after group-wise interleaving, that is, Y₂₉=X_(πp(29))=X₂₀, Y₃₀=X_(πp(30))=X₂₄, Y₃₁=X_(πp(31))=X₄₄, . . . , Y₄₂=X_(πp(42))=X₂₈, Y₄₃=X_(πp(43))=X₃₉, Y₄₄=X_(πp(44))=X₄₂ may be the second pattern.

Meanwhile, as described above, the second pattern defines bit groups always to be punctured in a current frame regardless of the shortening length, and the first pattern defines bit groups additionally to be punctured as the shortening length is long, such that the first pattern may be used to determine the LDPC parity bits transmitted in the current frame after the puncturing.

In detail, according to the number of LDPC parity bits to be punctured, in addition to the LDPC parity bits always to be punctured, more LDPC parity bits may additionally be punctured.

For example, in the L1-detail mode 2, when the number of LDPC parity bits to be punctured is 7200, 20 bit groups need to be punctured, and thus, four (4) bit groups need to be additionally punctured, in addition to the 16 bit groups always to be punctured.

In this case, the additionally punctured four (4) bit groups correspond to the bit groups positioned at 25-th to 28-th positions after group-wise interleaving, and since these bit groups are determined according to the first pattern, that is, belong to the first pattern, the first pattern may be used to determine the punctured bit groups.

That is, when LDPC parity bits are punctured more than a minimum value of LDPC parity bits to be punctured, which bit groups are to be additionally punctured is determined according to which bit groups are positioned after the bit groups always to be punctured. As a result, according to a puncturing direction, the first pattern which defines the bit groups positioned after the bit groups always to be punctured may be considered as determining the punctured bit groups.

That is, as in the foregoing example, when the number of LDPC parity bits to be punctured is 7200, in addition to the 16 bit groups always to be punctured, four (4) bit groups, that is, the bit groups positioned at 28-th, 27-th, 26-th, and 25-th positions, after group-wise interleaving is performed, are additionally punctured. Here, the bit groups positioned at 25-th to 28-th positions after the group-wise interleaving are determined according to the first pattern.

As a result, the first pattern may be considered as being used to determine the bit groups to be punctured. Further, the remaining LDPC parity bits other than the punctured LDPC parity bits are transmitted through the current frame, and therefore, the first pattern may be considered as being used to determine the bit groups transmitted in the current frame.

Meanwhile, the second pattern may be used only to determine the additional parity bits transmitted in the previous frame.

In detail, since the bit groups determined as to be always punctured are always punctured, and then, are not transmitted in the current frame, these bit groups need to be positioned only where bits are always punctured after group-wise interleaving. Therefore, it is not important at which position of these bit groups are positioned therebetween.

For example, in the L1-detail mode 2, bit groups positioned at 20-th, 24-th, 44-th, . . . , 28-th, 39-th and 42-th positions before the group-wise interleaving need to be positioned only at a 29-th bit group to a 44-th bit group after the group-wise interleaving. Therefore, it is not important at which positions of these bit groups are positioned.

As such, the second pattern defining bit groups always to be punctured is used only to identify bit groups to be punctured. Therefore, defining an order between the bit groups in the second pattern is meaningless in the puncturing, and thus, the second pattern defining bit groups always to be punctured may be considered as not being used for the puncturing.

However, for determining additional parity bits, positions of the bit groups always to be punctured within these bit groups are considered.

In detail, since the additional parity bits are generated by selecting bits as many as a predetermined number from the first bit among the punctured LDPC parity bits, bits included in at least some of the bit groups always to be punctured may be selected as at least some of the additional parity bits depending on the number of punctured LDPC parity bits and the number of additional parity bits.

That is, when the additional parity bits are selected beyond the bit group defined according to the first pattern, since the additional parity bits are sequentially selected from a start portion of the second pattern, the order of the bit groups belonging to the second pattern is meaningful in terms of selection of the additional parity bits. As a result, the second pattern defining a bit group always to be punctured may be considered as being used to determine the additional parity bits.

For example, in the L1-detail mode 2, the total number of LDPC parity bits is 12960 and the number of bit groups always to be punctured is 16.

In this case, the second pattern may be used to generate the additional parity bits depending on whether a value obtained by subtracting the number of LDPC parity bits to be punctured from the number of all LDPC parity bits and adding the subtraction result to the number of additional parity bits exceeds 7200. Here, 7200 is the number of LDPC parity bits included in the remaining bit groups, other than the bit groups always to be punctured, among the bit groups configuring the LDPC parity bits. That is, 7200=(36−16)×360.

In detail, when the value obtained by the above subtraction and addition is equal to or less than 7200, that is, 12960−N_(punc)+N_(AP)≤7200, the additional parity bits may be generated according to the first pattern.

However, when the value obtained by the above subtraction and addition exceeds 7200, that is, 12960−N_(punc)+N_(AP)>7200, the additional parity bits may be generated according to the first pattern and the second pattern.

In detail, when 12960−N_(punc)+N_(AP)>7200, for the additional parity bits, bits included in the bit group positioned at a 28-th position from the first LDPC parity bit among the punctured LDPC parity bits may be selected, and bits included in the bit group positioned at a predetermined position from a 29-th position may be selected.

Here, the bit group to which the first LDPC parity bit among the punctured LDPC parity bits belongs and the bit group (that a bit group to which the finally selected LDPC parity bits belong when being sequentially selected from the first LDPC parity bit among the punctured LDPC parity bits) at the predetermined position may be determined according to the number of LDPC parity bits to be punctured and the number of additional parity bits.

In this case, the bit group positioned at a 28-th position from the firth LDPC parity bit among the punctured LDPC parity bits is determined according to the first pattern, and the bit group positioned at a predetermined position from a 29-th position is determined according to the second pattern.

As a result, the additional parity bits are determined according to the first pattern and the second pattern.

As such, the first pattern may be used to determine additional parity bits as well as LDPC parity bits to be punctured, but the second pattern may be used to determine only the additional parity bits.

Meanwhile, the foregoing example describes that the group-wise interleaving pattern includes the first pattern and the second pattern, which is only for convenience of explanation in terms of the puncturing and the additional parity. That is, the group-wise interleaving pattern may be considered as one pattern without being divided into the first pattern and the second pattern. In this case, the group-wise interleaving may be considered as being performed with one pattern both for the puncturing and the additional parity.

Meanwhile, the values used in the foregoing example such as the number of punctured LDPC parity bits are only example values.

The zero removers 218 and 321 may remove zero bits padded by the zero padders 213 and 314 from the LDPC codewords output from the puncturers 217 and 318, and output the remaining bits to the bit demultiplexers 219 and 322.

Here, the removal does not only remove the padded zero bits but also may include outputting the remaining bits other than the padded zero bits in the LDPC codewords.

In detail, the zero removers 218 and 321 may remove K_(ldpc)−N_(outer) zero bits padded by the zero padders 213 and 314. Therefore, the K_(ldpc)−N_(outer) padded zero bits are removed, and thus, may not be transmitted to the receiver 200.

For example, as illustrated in FIG. 26, it is assumed that all bits of a first bit group, a fourth bit group, a fifth bit group, a seventh bit group, and an eighth bit group among a plurality of bit groups configuring an LDPC codeword are padded by zero bits, and some bits of the second bit group are padded by zero bits.

In this case, the zero removers 218 and 321 may remove the zero bits padded to the first bit group, the second bit group, the fourth bit group, the fifth bit group, the seventh bit group, and the eighth bit group.

As such, when zero bits are removed, as illustrated in FIG. 26, an LDPC codeword formed of K_(sig) information bits (that is, K_(sig) L1-basic signaling bits and K_(sig) L1-detail signaling bits), 168 BCH parity check bits (that is, BCH FEC), and N_(inner)−K_(ldpc)−N_(punc) or N_(inner)−K_(ldpc)−N_(punc)+N_(repeat) parity bits may remain.

That is, when repetition is performed, the lengths of all the LDPC codewords become N_(FEC)+N_(repeat). Here, N_(FEC)=N_(outer)+N_(ldpc_parity)−N_(punc). However, in a mode in which the repetition is not performed, the lengths of all the LDPC codewords become N_(FEC).

The bit demultiplexers 219 and 322 may interleave the bits output from the zero removers 218 and 321, demultiplex the interleaved bits, and then output them to the constellation mappers 221 and 324.

For this purpose, the bit demultiplexers 219 and 322 may include a block interleaver (not illustrated) and a demultiplexer (not illustrated).

First, a block interleaving scheme performed in the block interleaver is illustrated in FIG. 27.

In detail, the bits of the N_(FEC) or N_(FEC)+N_(repeat) length after the zero bits are removed may be column-wisely serially written in the block interleaver. Here, the number of columns of the block interleaver is equivalent to the modulation order and the number of rows is N_(FEC)/η_(MOD) or (N_(FEC)+N_(repeat))/η_(MOD).

Further, in a read operation, bits for one constellation symbol may be sequentially read in a row direction to be input to the demultiplexer. The operation may be continued to the last row of the column.

That is, the N_(FEC) or (N_(FEC)+N_(repeat)) bits may be written in a plurality of columns in a column direction from the first row of the first column, and the bits written in the plurality of columns are sequentially read from the first row to the final row of the plurality of columns in a row direction. In this case, the bits read in the same row may configure one modulation symbol.

Meanwhile, the demultiplexer may demultiplex the bits output from the block interleaver.

In detail, the demultiplexer may demultiplex each of the block-interleaved bit groups, that is, the bits output while being read in the same row of the block interleaver within the bit group bit-by-bit, before the bits are mapped to constellation.

In this case, two mapping rules may be present according to the modulation order.

In detail, when QPSK is used for modulation, since reliability of bits within a constellation symbol is the same, the demultiplexer does not perform the demultiplexing operation on a bit group. Therefore, the bit group read and output from the block interleaver may be mapped to a QPSK symbol without the demultiplexing operation.

However, when high order modulation is used, the demultiplexer may perform demultiplexing on a bit group read and output from the block interleaver based on following Equation 28. That is, a bit group may be mapped to a QAM symbol depending on following Equation 28.

S _(demux_in(i)) ={b _(i)(0),b _(i)(1),b _(i)(2), . . . ,b _(i)(η_(MOD)−1)},

S _(demux_out(i)) ={c _(i)(0),c _(i)(1),c _(i)(2), . . . ,c _(i)(η_(MOD)−1)},

c _(i)(0)=b _(i)(i%η_(MOD)),c _(i)(1)=b _(i)(i+1)%η_(MOD)), . . . ,c _(i)(η_(MOD)−1)=b _(i)((i+η _(MOD)−1)%η_(MOD))  (28)

In above Equation 28, % represents a modulo operation, and η_(MOD) is a modulation order.

Further, i is a bit group index corresponding to a row index of the block interleaver. That is, an output bit group S_(demux_out(i)) mapped to each of the QAM symbols may be cyclic-shifted in an S_(demux_in(i)) according to the bit group index i.

Meanwhile, FIG. 28 illustrates an example of performing bit demultiplexing on 16-non uniform constellation (16-NUC), that is, NUC 16-QAM. The operation may be continued until all bit groups are read in the block interleaver.

Meanwhile, the bit demultiplexer 323 may perform the same operation, as the operations performed by the bit demultiplexers 219 and 322, on the additional parity bits output from the additional parity generator 319, and output the block-interleaved and demultiplexed bits to the constellation mapper 325.

The constellation mappers 221, 324 and 325 may map the bits output from the bit demultiplexers 219, 322 and 323 to constellation symbols, respectively.

That is, each of the constellation mappers 221, 324 and 325 may map the S_(demux_out(i)) to a cell word using constellation according to a corresponding mode. Here, the S_(demux_out(i)) may be configured of bits having the same number as the modulation order.

In detail, the constellation mappers 221, 324 and 325 may map bits output from the bit demultiplexers 219, 322 and 323 to constellation symbols using QPSK, 16-QAM, 64-QAM, the 256-QAM, etc., according to a corresponding mode.

In this case, the constellation mappers 221, 324 and 325 may use the NUC. That is, the constellation mappers 221, 324 and 325 may use NUC 16-QAM, NUC 64-QAM or NUC 256-QAM. Meanwhile, the modulation scheme applied to the L1-basic signaling and the L1-detail signaling according to a corresponding mode is shown in above Table 4.

Meanwhile, the transmitter 100 may map the constellation symbols to a frame and transmit the mapped symbols to the receiver 200.

In detail, the transmitter 100 may map the constellation symbols corresponding to each of the L1-basic signaling and the L1-detail signaling output from the constellation mappers 221 and 324, and map the constellation symbols corresponding to the additional parity bits output from the constellation mapper 325 to a preamble symbol of a frame.

In this case, the transmitter 100 may map the additional parity bits generated based on the L1-detail signaling transmitted in the current frame to a frame before the corresponding frame.

That is, the transmitter 100 may map the LDPC codeword bits including the L1-basic signaling corresponding to the (i−1)-th frame to the (i−1)-th frame, maps the LDPC codeword bits including the L1-detail signaling corresponding to the (i−1)-th frame to the (i−1)-th frame, and additionally map the additional parity bits generated selected from the LDPC parity bits generated based on the L1-detail signaling corresponding to the i-th frame to the (i−1)-th frame and may transmit the mapped bits to the receiver 200.

In addition, the transmitter 100 may map data to the data symbols of the frame in addition to the L1 signaling and transmit the frame including the L1 signaling and the data to the receiver 200.

In this case, since the L1 signalings include signaling information about the data, the signaling about the data mapped to each data may be mapped to a preamble of a corresponding frame. For example, the transmitter 100 may map the L1 signaling including the signaling information about the data mapped to the i-th frame to the i-th frame.

As a result, the receiver 200 may use the signaling obtained from the frame to receive the data from the corresponding frame for processing.

Meanwhile, the foregoing example describes that the repeaters 120, 216 and 317 calculate the number of bits to be repeated based on above Equations 8 and 21, which is only an example. The repeaters 120, 216 and 317 may calculate the number of bits to be repeated by various other methods. Hereinafter, it is assumed that K_(ldpc)=3240, N_(ldpc_parity)=12960 and η_(MOD)=2.

For example, the repeaters 120, 216 and 317 may calculate the number N_(repeat) of LDPC parity bits additionally transmitted per LDPC codeword based on following Equation 29 or 30.

$\begin{matrix} {N_{repeat} = {{\eta_{MOD} \times \left\lfloor \frac{C \times N_{outer}}{\eta_{MOD}} \right\rfloor} + D}} & (29) \\ {N_{repeat} = {{\eta_{MOD} \times \left\lfloor \frac{C \times K_{sig}}{\eta_{MOD}} \right\rfloor} + D^{\prime}}} & (30) \end{matrix}$

Here, C may have a fixed value, and D and D′ may be integer constants, respectively (in detail, even number).

Referring to Equations 29 and 30, according to a corresponding mode, the number of bits to be repeated may be calculated by multiplying C and adding D or D′.

For example, the parameters C, D and D′ values for the repetition are C=61/8, D=−508 and D′=772.

Further, the repeaters 120, 216 and 317 may calculate a size N_(FEC_REP) of one coded block based on following Equation 31.

N _(FEC_REP) =N _(FEC) +N _(repeat)  (31)

If a length of a BCH encoded L1-detail signaling is fixed as 2N_(A), above Equation 29 may be represented like following Equation 32, and above Equation 30 may be represented like following Equation 33.

$\begin{matrix} {N_{repeat} = {{2 \times \left\lfloor {N_{A} \times C} \right\rfloor} + D}} & (32) \\ {N_{repeat} = {{2 \times \left\lfloor {\left( {N_{A} - \frac{M_{outer}}{2}} \right) \times C} \right\rfloor} + D^{\prime}}} & (33) \end{matrix}$

Here, for example, if a length of an L1-detail signaling is fixed as 200, above Equation 32 may be represented like following Equation 34, and above Equation 33 may be represented like following Equation 35.

N _(repeat)=2×└184×C┘+D  (34)

N _(repeat)=2×└100×C┘+D′  (35)

As a result, when η_(MOD) is 2, above Equation 34 may be represented like following Equation 36, and above Equation 35 may be represented like following Equation 37.

N _(repeat)=2×└C′×N _(outer) +D  (36)

N _(repeat)=2×└C′×K _(sig) ┘+D′  (37)

In this case, the parameters C′ (=C/2), D and D′ values for the repetition are C′=61/16, D=−508 and D′=772.

Meanwhile, if the length of the BCH encoded L1-detail signaling is fixed as 2N_(A), above Equation 32 may be represented like following Equation 38, and above Equation 33 may be represented like following Equation 39.

N _(repeat)=2×└2N _(A) ×C′┘+D′  (38)

N _(repeat)=2×└(2N _(A)−168)×C′┘+D′  (39)

Here, for example, if the length of the L1-detail signaling is fixed as 200, above Equation 38 may be represented like following Equation 40, and above Equation 39 may be represented like following Equation 41.

N _(repeat)=2×└368×C′┘+D  (40)

N _(repeat)=2×└200×C′┘+D′  (41)

As a result, when η_(MOD) is 2 and C is E/2^(m) (here, E and m are positive integers, respectively), above Equation 40 may be represented like following Equation 42, and above Equation 41 may be represented like following Equation 43.

$\begin{matrix} {N_{repeat} = {{{2 \times \left\lfloor {C^{\prime} \times N_{outer}} \right\rfloor} + D} = {{2 \times \left\lfloor {\frac{E}{2^{m + 1}} \times N_{outer}} \right\rfloor} + D}}} & (42) \\ {N_{repeat} = {{{2 \times \left\lfloor {C^{\prime} \times K_{sig}} \right\rfloor} + D^{\prime}} = {{2 \times \left\lfloor {\frac{E}{2^{m + 1}} \times K_{sig}} \right\rfloor} + D^{\prime}}}} & (43) \end{matrix}$

As another example, the repeaters 120, 216 and 317 may calculate the number N_(repeat) of LDPC parity bits additionally transmitted per LDPC codeword based on following Equation 44 or 45.

$\begin{matrix} {N_{repeat} = {\eta_{MOD} \times \left\lfloor \frac{\left\lfloor {C \times N_{outer}} \right\rfloor + D}{\eta_{MOD}} \right\rfloor}} & (44) \\ {N_{repeat} = {\eta_{MOD} \times \left\lfloor \frac{\left\lfloor {C \times K_{sig}} \right\rfloor + D^{\prime}}{\eta_{MOD}} \right\rfloor}} & (45) \end{matrix}$

Here, C may have a fixed value, and D and D′ may be integers, respectively.

Referring to Equations 44 and 45, according to a corresponding mode, the number of bits to be repeated may be calculated by multiplying C and adding D or D′.

For example, the parameters C, D and D′ values for the repetition are C=61/16, D=−508 and D′=772. Here, C may be equal to E/2^(m) (E and m are positive integers, respectively).

Further, the repeaters 120, 216 and 317 may calculate the size N_(FEC_REP) of one coded block based on following Equation 46.

N _(FEC_REP) =N _(FEC) +N _(repeat)  (46)

As another example, the repeaters 120, 216 and 317 may calculate the number N_(repeat) of LDPC parity bits additionally transmitted per LDPC codeword based on following Equation 47 or 48.

$\begin{matrix} {N_{repeat} = {{\eta_{MOD} \times \left\lfloor \frac{C \times N_{outer}}{\eta_{MOD}} \right\rfloor} + D}} & (47) \\ {N_{repeat} = {\eta_{MOD} \times \left\lfloor \frac{{C \times N_{outer}} + D^{\prime}}{\eta_{MOD}} \right\rfloor}} & (48) \end{matrix}$

Here, C may have a fixed value, and D and D′ may be integers, respectively.

Referring to Equations 47 and 48, according to a corresponding mode, the number of bits to be repeated may be calculated by multiplying C and adding D or D′.

For example, the parameters C, D and D′ values for the repetition are C=61/16, D=−508 and D′=772. Here, C may be equal to E/2^(m) (E and m are positive integers, respectively).

Further, the repeaters 120, 216, and 317 may calculate the size N_(FEC_REP) of one coded block based on following Equation 49.

N _(FEC_REP) =N _(FEC) +N _(repeat)  (49)

As another example, the repeaters 120, 216 and 317 may calculate the number N_(repeat) of LDPC parity bits additionally transmitted per the LDPC codeword based on following Equation 50, 51, 52 or 53.

$\begin{matrix} {N_{repeat} = {{\eta_{MOD} \times \left\lfloor \frac{C \times N_{outer}}{\eta_{MOD}} \right\rfloor} + D}} & (50) \\ {N_{repeat} = {{\eta_{MOD} \times \left\lfloor {C^{\prime} \times N_{outer}} \right\rfloor} + D}} & (51) \\ {N_{repeat} = {{\eta_{MOD} \times \left\lfloor \frac{C \times K_{sig}}{\eta_{MOD}} \right\rfloor} + D^{\prime}}} & (52) \\ {N_{repeat} = {{\eta_{MOD} \times \left\lfloor {C^{\prime} \times K_{sig}} \right\rfloor} + D^{\prime}}} & (53) \end{matrix}$

Here, C may have a fixed value, and D and D′ may be integers, respectively.

Referring to above Equations 50 to 53, according to a corresponding mode, the number of bits to be repeated may be calculated by multiplying C and adding D or D′, and D or D′ may be a multiple of common multiple of η_(MOD).

For example, when η_(MOD)=2, 4 and 6, D or D′ may be a multiple of 12, and when η MOD=2, 4, 6 and 8, D or D′ may be a multiple of 24.

For example, the parameters C, C′, D and D′ values for the repetition are C=61/8, C′=61/16, D=−504 and D′=768.

Further, the repeaters 120, 216 and 317 may calculate the size N_(FEC_REP) of one coded block based on following Equation 54.

N _(FEC_REP) =N _(FEC) +N _(repeat)  (54)

Meanwhile, various repetition methods will be additionally described below.

For example, it is assumed that N_(repeat)≥N_(punc) and N_(repeat)≤N_(ldpc_parity). In this case, the repeaters 120, 216 and 317 may select N_(repeat) bits from the LDPC parity bits as illustrated in FIG. 29, and may add the selected N_(repeat) bits after the LDPC parity bits from which N_(punc) bits are removed by puncturing.

As another example, it is assumed that N_(repeat)≤N_(punc) and N_(repeat)<N_(ldpc_parity). In this case, the repeaters 120, 216 and 317 may select N_(repeat) bits from the LDPC parity bits which are not punctured as illustrated in FIG. 30, and may add the selected N_(repeat) bits after the LDPC parity bits from which N_(punc) bits are removed by puncturing.

As another example, it is assumed that N_(repeat)>N_(ldpc_parity). In this case, the repeaters 120, 216 and 317 may select all the LDPC parity bits and N_(repeat)−N_(ldpc_parity) LDPC parity bits from the LDPC parity bits which are not punctured as illustrated in FIG. 31, and may add the selected N_(repeat) bits after the LDPC parity bits from which N_(punc) bits are removed by the puncturing.

As such, according to various exemplary embodiments, LDPC codeword bits may be repeated by various methods.

FIGS. 32 and 33 are block diagrams for describing a configuration of a receiver according to an exemplary embodiment.

In detail, as illustrated in FIG. 32, the receiver 200 may include a constellation demapper 2510, a multiplexer 2520, a Log Likelihood Ratio (LLR) inserter 2530, an LLR combiner 2540, a parity depermutator 2550, an LDPC decoder 2560, a zero remover 2570, a BCH decoder 2580, and a descrambler 2590 to process the L1-basic signaling.

Further, as illustrated in FIG. 33, the receiver 200 may include constellation demappers 2611 and 2612, multiplexers 2621 and 2622, an LLR inserter 2630, an LLR combiner 2640, a parity depermutator 2650, an LDPC decoder 2660, a zero remover 2670, a BCH decoder 2680, a descrambler 2690, and a desegmenter 2695 to process the L1-detail signaling.

Here, the components illustrated in FIGS. 32 and 33 are components performing functions corresponding to the functions of components illustrated in FIGS. 13 and 14, respectively, which is only an example, and in some cases, some of the components may be omitted and changed and other components may be added.

The receiver 200 may acquire frame synchronization using a bootstrap of a frame and receive L1-basic signaling from a preamble of the frame using information for processing the L1-basic signaling included in the bootstrap.

Further, the receiver 200 may receive L1-detail signaling from the preamble using information for processing the L1-detail signaling included in the L1-basic signaling, and receive broadcasting data required by a user from data symbols of the frame using the L1-detail signaling.

Therefore, the receiver 200 may determine a mode of used at the transmitter 100 to process the L1-basic signaling and the L1-detail signaling, and process a signal received from the transmitter 100 according to the determined mode to receive the L1-basic signaling and the L1-detail signaling. For this purpose, the receiver 200 may pre-store information about parameters used at the transmitter 100 to process the signaling according to corresponding modes.

As such, the L1-basic signaling and the L1-detail signaling may be sequentially acquired from the preamble. In describing FIGS. 58 and 59, components performing common functions will be described together for convenience of explanation.

The constellation demappers 2510, 2611 and 2612 demodulate a signal received from the transmitter 100.

In detail, the constellation demappers 2510, 2611 and 2612 are components corresponding to the constellation mappers 221, 324 and 325 of the transmitter 100, respectively, and may demodulate the signal received from the transmitter 100 and generate values corresponding to bits transmitted from the transmitter 100.

That is, as described above, the transmitter 100 maps an LDPC codeword including the L1-basic signaling and the LDPC codeword including the L1-detail signaling to the preamble of a frame, and transmits the mapped LDPC codeword to the receiver 200. Further, in some cases, the transmitter 100 may map additional parity bits to the preamble of a frame and transmit the mapped bits to the receiver 200.

As a result, the constellation demappers 2510 and 2611 may generate values corresponding to the LDPC codeword bits including the L1-basic signaling and the LDPC codeword bits including the L1-detail signaling. Further, the constellation demapper 2612 may generate values corresponding to the additional parity bits.

For this purpose, the receiver 200 may pre-store information about a modulation scheme used by the transmitter 100 to modulate the L1-basic signaling, the L1-detail signaling, and the additional parity bits according to corresponding modes. Therefore, the constellation demappers 2510, 2611 and 2612 may demodulate the signal received from the transmitter 100 according to the corresponding modes to generate values corresponding to the LDPC codeword bits and the additional parity bits.

Meanwhile, the value corresponding to a bit transmitted from the transmitter 100 is a value calculated based on probability that a received bit is 0 and 1, and instead, the probability itself may also be used as a value corresponding to each bit. The value may also be a Likelihood Ratio (LR) or an LLR value as another example.

In detail, an LR value may represent a ratio of probability that a bit transmitted from the transmitter 100 is 0 and probability that the bit is 1, and an LLR value may represent a value obtained by taking a log on probability that the bit transmitted from the transmitter 100 is 0 and probability that the bit is 1.

Meanwhile, it is described that the foregoing example uses the LR value or the LLR value, which is only one example. According to another exemplary embodiment, the received signal itself rather than the LR or LLR value may also be used.

The multiplexers 2520, 2621 and 2622 perform multiplexing on LLR values output from the constellation demappers 2510, 2611 and 2612.

In detail, the multiplexers 2520, 2621 and 2622 are components corresponding to the bit demultiplexers 219, 322 and 323 of the transmitter 100, and may perform operations corresponding to the operations of the bit demultiplexers 219, 322 and 323, respectively.

For this purpose, the receiver 200 may pre-store information about parameters used for the transmitter 100 to perform demultiplexing and block interleaving. Therefore, the multiplexers 2520, 2621 and 2622 may reversely perform the demultiplexing and block interleaving operations of the bit demultiplexers 219, 322 and 323 on the LLR value corresponding to a cell word to multiplex the LLR value corresponding to the cell word in a bit unit.

The LLR inserters 2530 and 2630 may insert LLR values for the puncturing and shortening bits into the LLR values output from the multiplexers 2520 and 2621, respectively. In this case, the LLR inserters 2530 and 2630 may insert predetermined LLR values between the LLR values output from the multiplexers 2520 and 2621 or a head portion or an end portion thereof.

In detail, the LLR inserters 2530 and 2630 are components corresponding to the zero removers 218 and 321 and the puncturers 217 and 318 of the transmitter 100, respectively, and may perform operations corresponding to the operations of the zero removers 218 and 321 and the puncturers 217 and 318, respectively.

First, the LLR inserters 2530 and 2630 may insert LLR values corresponding to zero bits into a position where the zero bits in an LDPC codeword are padded. In this case, the LLR values corresponding to the padded zero bits, that is, the shortened zero bits may be ∞ or −∞. However, ∞ or −∞ are a theoretical value but may actually be a maximum value or a minimum value of the LLR value used in the receiver 200.

For this purpose, the receiver 200 may pre-store information about parameters and/or patterns used for the transmitter 100 to pad the zero bits according to corresponding modes. Therefore, the LLR inserters 2530 and 2630 may determine positions where the zero bits in the LDPC codewords are padded according to the corresponding modes, and insert the LLR values corresponding to the shortened zero bits into corresponding positions.

Further, the LLR inserters 2530 and 2630 may insert the LLR values corresponding to the punctured bits into the positions of the punctured bits in the LDPC codeword. In this case, the LLR values corresponding to the punctured bits may be 0.

For this purpose, the receiver 200 may pre-store information about parameters and/or patterns used for the transmitter 100 to perform puncturing according to corresponding modes. Therefore, the LLR inserters 2530 and 2630 may determine the lengths of the punctured LDPC parity bits according to the corresponding modes, and insert corresponding LLR values into the positions where the LDPC parity bits are punctured.

Meanwhile, in a case of additional parity bits selected from the punctured bits among the additional parity bits, the LLR inserter 2630 may insert LLR values corresponding to the received additional parity bits, not an LLR value ‘0’ for the punctured bit, into the positions of the punctured bits.

The LLR combiners 2540 and 2640 may combine, that is, a sum the LLR values output from the LLR inserters 2530 and 2630 and the LLR value output from the multiplexer 2622. However, the LLR combiners 2540 and 2640 serve to update LLR values for specific bits into more correct values. However, the LLR values for the specific bits may also be decoded from the received LLR values without the LLR combiners 2540 and 2640, and therefore, in some cases, the LLR combiners 2540 and 2640 may be omitted.

In detail, the LLR combiner 2540 is a component corresponding to the repeater 216 of the transmitter 100, and may perform an operation corresponding to the operation of the repeater 216. Alternatively, the LLR combiner 2640 is a component corresponding to the repeater 317 and the additional parity generator 319 of the transmitter 100, and may perform operations corresponding to the operations of the repeater 317 and the additional parity generator 319.

First, the LLR combiners 2540 and 2640 may combine LLR values corresponding to the repetition bits with other LLR values. Here, the other LLR values may be bits which are a basis of generating the repetition bits by the transmitter 100, that is, LLR values for the LDPC parity bits selected as the repeated object.

That is, as described above, the transmitter 100 selects bits from the LDPC parity bits and repeats the selected bits between the LDPC information bits and the LDPC parity bits generated by LDPC encoding, and transmits the repetition bits to the receiver 200.

As a result, the LLR values for the LDPC parity bits may be formed of the LLR values for the repeated LDPC parity bits and the LLR values for the non-repeated LDPC parity bits, that is, the LDPC parity bits generated by the LDPC encoding. Therefore, the LLR combiners 2540 and 2640 may combine the LLR values for the same LDPC parity bits.

For this purpose, the receiver 200 may pre-store information about parameters used for the transmitter 100 to perform the repetition according to corresponding modes. As a result, the LLR combiners 2540 and 2640 may determine the lengths of the repeated LDPC parity bits, determine the positions of the bits which are a basis of the repetition, and combine the LLR values for the repeated LDPC parity bits with the LLR values for the LDPC parity bits which are a basis of the repetition and generated by the LDPC encoding.

For example, as illustrated in FIGS. 34 and 35, the LLR combiners 2540 and 2640 may combine LLR values for repeated LDPC parity bits with LLR values for LDPC parity bits which are a basis of the repetition and generated by the LDPC encoding.

Meanwhile, when LPDC parity bits are repeated n times, the LLR combiners 2540 and 2640 may combine LLR values for bits at the same position at n times or less.

For example, FIG. 34 illustrates a case in which some of LDPC parity bits other than punctured bits are repeated once. In this case, the LLR combiners 2540 and 2640 may combine LLR values for the repeated LDPC parity bits with LLR values for the LDPC parity bits generated by the LDPC encoding, and then, output the combined LLR values or output the LLR values for the received repeated LDPC parity bits or the LLR values for the received LDPC parity bits generated by the LDPC encoding without combining them.

As another example, FIG. 35 illustrates a case in which some of the transmitted LDPC parity bits, which are not punctured, are repeated twice, the remaining portion is repeated once, and the punctured LDPC parity bits are repeated once.

In this case, the LLR combiners 2540 and 2640 may process the remaining portion and the pictured bits which are repeated once by the same scheme as described above. However, the LLR combiners 2540 and 2640 may process the portion repeated twice as follows. In this case, for convenience of description, one of the two portions generated by repeating some of the LDPC parity bits twice is referred to as a first portion and the other is referred to as the second portion.

In detail, the LLR combiners 2540 and 2640 may combine LLR values for each of the first and second portions with LLR values for the LDPC parity bits. Alternatively, the LLR combiners 2540 and 2640 may combine the LLR values for the first portion with the LLR values for the LDPC parity bits, combine the LLR values for the second portion with the LLR values for the LDPC parity bits, or combine the LLR values for the first portion with the LLR values for the second portion. Alternatively, the LLR combiners 2540 and 2640 may output the LLR values for the first portion, the LLR values for the second portion, the LLR values for the remaining portion, and punctured bits, without separate combination.

Further, the LLR combiner 2640 may combine LLR values corresponding to additional parity bits with other LLR values. Here, the other LLR values may be the LDPC parity bits which are a basis of the generation of the additional parity bits by the transmitter 100, that is, the LLR values for the LDPC parity bits selected for generation of the additional parity bits.

That is, as described above, the transmitter 100 may map additional parity bits for L1-detail signaling transmitted in a current frame to a previous frame and transmit the mapped bits to the receiver 200.

In this case, the additional parity bits may include LDPC parity bits which are punctured and are not transmitted in the current frame, and in some cases, may further include LDPC parity bits transmitted in the current frame.

As a result, the LLR combiner 2640 may combine LLR values for the additional parity bits received through the current frame with LLR values inserted into the positions of the punctured LDPC parity bits in the LDPC codeword received through the next frame and LLR values for the LDPC parity bits received through the next frame.

For this purpose, the receiver 200 may pre-store information about parameters and/or patterns used for the transmitter 100 to generate the additional parity bits according to corresponding modes. As a result, the LLR combiner 2640 may determine the lengths of the additional parity bits, determine the positions of the LDPC parity bits which are a basis of generation of the additional parity bits, and combine the LLR values for the additional parity bits with the LLR values for the LDPC parity bits which are a basis of generation of the additional parity bits.

The parity depermutators 2550 and 2650 may depermutate the LLR values output from the LLR combiners 2540 and 2640, respectively.

In detail, the parity depermutators 2550 and 2650 are components corresponding to the parity permutators 215 and 316 of the transmitter 100, and may perform operations corresponding to the operations of the parity permutators 215 and 316, respectively.

For this purpose, the receiver 200 may pre-store information about parameters and/or patterns used for the transmitter 100 to perform group-wise interleaving and parity interleaving according to corresponding modes. Therefore, the parity depermutators 2550 and 2650 may reversely perform the group-wise interleaving and parity interleaving operations of the parity permutators 215 and 316 on the LLR values corresponding to the LDPC codeword bits, that is, perform group-wise deinterleaving and parity deinterleaving operations to perform the parity depermutation on the LLR values corresponding to the LDPC codeword bits, respectively.

The LDPC decoders 2560 and 2660 may perform LDPC decoding based on the LLR values output from the parity depermutators 2550 and 2650, respectively.

In detail, the LDPC decoders 2560 and 2660 are components corresponding to the LDPC encoders 214 and 315 of the transmitter 100 and may perform operations corresponding to the operations of the LDPC encoders 214 and 315, respectively.

For this purpose, the receiver 200 may pre-store information about parameters used for the transmitter 100 to perform the LDPC encoding according to corresponding modes. Therefore, the LDPC decoders 2560 and may perform the LDPC decoding based on the LLR values output from the parity depermutators 2550 and 2650 according to the corresponding modes.

For example, the LDPC decoders 2560 and 2660 may perform the LDPC decoding based on the LLR values output from the parity depermutators 2550 and 2650 by iterative decoding based on a sum-product algorithm and output error-corrected bits depending on the LDPC decoding.

The zero removers 2570 and 2670 may remove zero bits from the bits output from the LDPC decoders 2560 and 2660, respectively.

In detail, the zero removers 2570 and 2670 are components corresponding to the zero padders 213 and 314 of the transmitter 100, and may perform operations corresponding to the operations of the zero padders 213 and 314, respectively.

For this purpose, the receiver 200 may pre-store information about parameters and/or patterns used for the transmitter 100 to pad the zero bits according to corresponding modes. As a result, the zero removers 2570 and 2670 may remove the zero bits padded by the zero padders 213 and 314 from the bits output from the LDPC decoders 2560 and 2660, respectively.

The BCH decoders 2580 and 2680 may perform BCH decoding on the bits output from the zero removers 2570 and 2670, respectively.

In detail, the BCH decoders 2580 and 2680 are components corresponding to the BCH encoders 212 and 313 of the transmitter 100, and may perform operations corresponding to the operations of the BCH encoders 212 and 313, respectively.

For this purpose, the receiver 200 may pre-store the information about parameters used for the transmitter 100 to perform BCH encoding. As a result, the BCH decoders 2580 and 2680 may correct errors by performing the BCH decoding on the bits output from the zero removers 2570 and 2670 and output the error-corrected bits.

The descramblers 2590 and 2690 may descramble the bits output from the BCH decoders 2580 and 2680, respectively.

In detail, the descramblers 2590 and 2690 are components corresponding to the scramblers 211 and 312 of the transmitter 100, and may perform operations corresponding to the operations of the scramblers 211 and 312.

For this purpose, the receiver 200 may pre-store information about parameters used for the transmitter 100 to perform scrambling. As a result, the descramblers 2590 and 2690 may descramble the bits output from the BCH decoders 2580 and 2680 and output them, respectively.

As a result, L1-basic signaling transmitted from the transmitter 100 may be recovered. Further, when the transmitter 100 does not perform segmentation on L1-detail signaling, the L1-detail signaling transmitted from the transmitter 100 may also be recovered.

However, when the transmitter 100 performs the segmentation on the L1-detail signaling, the desegmenter 2695 may desegment the bits output from the descrambler 2690.

In detail, the desegmenter 2695 is a component corresponding to the segmenter 311 of the transmitter 100, and may perform an operation corresponding to the operation of the segmenter 311.

For this purpose, the receiver 200 may pre-store information about parameters used for the transmitter 100 to perform the segmentation. As a result, the desegmenter 2695 may combine the bits output from the descrambler 2690, that is, the segments for the L1-detail signaling to recover the L1-detail signaling before the segmentation.

Meanwhile, the information about the length of the L1 signaling is provided as illustrated in FIG. 36. Therefore, the receiver 200 may calculate the length of the L1-detail signaling and the length of the additional parity bits.

Referring to FIG. 36, since the L1-basic signaling provides information about L1-detail total cells, the receiver 200 needs to calculate the length of the L1-detail signaling and the lengths of the additional parity bits.

In detail, when L1B_L1_Detail_additional_parity_mode of the L1-basic signaling is not 0, since the information on the given L1B_L1_Detail_total_cells represents a total cell length (=N_(L1_detail_total_cells)), the receiver 200 may calculate the length N_(L1_detail_cells) of the L1-detail signaling and the length N_(AP_total_cells) of the additional parity bits based on following Equations 55 to 58.

$\begin{matrix} {N_{L\; 1\_\;{FEC}\;\_\;{cells}} = {\frac{N_{outer} + N_{repeat} + N_{{ldpc}\;\_\;{parity}} - N_{punc}}{\eta_{MOD}} = \frac{N_{FEC}}{\eta_{MOD}}}} & (55) \\ {N_{L\; 1\_\;{detail}\;\_\;{cells}} = {N_{L\; 1D\;\_\;{FECFRAME}} \times N_{L\; 1\_\;{FEC}\;\_\;{cells}}}} & (56) \\ {N_{{AP}\;\_\;{total}\;\_\;{cells}} = {N_{L\; 1\_\;{detail}\;\_\;{total}\;\_\;{cells}} - N_{L\; 1\_\;{detail}\;\_\;{cells}}}} & (57) \end{matrix}$

In this case, based on above Equations 55 to 57, an N_(AP_total_cells) value may be obtained based on an N_(L1_detail_total_cells) value which may be obtained from the information about the L1B_L1_Detail_total_cells of the L1-basic signaling, N_(FEC), the N_(L1D_FECFRAME), and the modulation order f_(M)OD. As an example, N_(AP_total_cells) may be calculated based on following Equation 58.

$\begin{matrix} {N_{{AP}\;\_\;{total}\;\_\;{cells}} = {N_{L\; 1\_\;{detail}\;\_\;{total}\;\_\;{cells}} - {N_{L\; 10\_\;{FECFRAME}} \times \frac{N_{FEC}}{\eta_{MOD}}}}} & \left\lbrack {{Equation}\mspace{14mu} 58} \right\rbrack \end{matrix}$

Meanwhile, a syntax, and field semantics of the L1-basic signaling field are as following Table 13.

TABLE 13 Syntax # of bits Format L1_Basic_signaling( ) {  L1B_L1_Detail_size_bits 16 uimsbf  L1B_L1_Detail_fec_type  3 uimsbf  L1B_L1_Detail_additional_parity_mode  2 uimsbf  L1B_L1_Detail_total_cells 19 uimsbf  L1B_Reserved ? uimsbf  L1B_crc 32 uimsbf {

As a result, the receiver 200 may perform an operation of a receiver for the additional parity bits in a next frame based on the additional parity bits transmitted to the N_(AP_total_cells) cell among the received L1 detail cells.

FIG. 37 is a flow chart for describing a repetition method according to an exemplary embodiment.

First, an LDPC codeword including parity bits are generated by encoding input bits (S3110).

Next, at least some bits from the LDPC codeword formed of the input bits and the parity bits are selected, and the selected some bits are added as repetition bits after the input bits (S3120).

Further, some of the parity bits are punctured (S3130).

Here, the input bits may include padded zero bits, and in operation S3120, the number of added bits may be calculated based on the number of bits other than the padded zero bits in the input bits.

Further, the input bits include outer encoded bits, and in operation S3120, the number of added bits may be calculated based on the number of outer encoded bits. In this case, the number of added bits may be calculated based on above Equation 8, and in above Equation 8, D may be even number.

Meanwhile, in operation S3120, when the calculated number of bits is equal to or less than the number of parity bits, bits as many as the calculated number from the first parity bit of the parity bits may be selected and the selected bits may be added after the input bits.

Further, in operation S3120, when the calculated number of bits is greater than the number of parity bits, all the parity bits are selected and the selected parity bits are added after the input bits and bits as many as the number obtained by subtracting the number of parity bits from the calculated number of bits from the first parity bit may be selected and the selected bits may be added after the added parity bits.

Meanwhile, the detailed description of the repetition is described above, and thus, duplicate descriptions are omitted.

Meanwhile, a non-transitory computer readable medium in which a program sequentially executing the various methods described above may be stored may be provided according to an exemplary embodiment. The non-transitory computer readable medium is not a medium that stores data therein for a while, such as a register, a cache, a memory, or the like, but means a medium that at least semi-permanently stores data therein and is readable by a device such as a microprocessor. In detail, various applications or programs described above may be stored and provided in the non-transitory computer readable medium such as a compact disk (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, a read only memory (ROM), or the like.

At least one of the components, elements, modules or units represented by a block as illustrated in FIGS. 1, 13, 14, 32 and 33 may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to an exemplary embodiment. For example, at least one of these components, elements, modules or units may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of these components, elements, modules or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Also, at least one of these components, elements, modules or units may further include or implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of these components, elements, modules or units may be combined into one single component, element, module or unit which performs all operations or functions of the combined two or more components, elements, modules or units. Also, at least part of functions of at least one of these components, elements, modules or units may be performed by another of these components, elements, modules or units. Further, although a bus is not illustrated in the above block diagrams, communication between the components, elements, modules or units may be performed through the bus. Functional aspects of the above exemplary embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements, modules or units represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

Although the exemplary embodiments of inventive concept have been illustrated and described hereinabove, the inventive concept is not limited to the above-mentioned exemplary embodiments, but may be variously modified by those skilled in the art to which the inventive concept pertains without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims. For example, the exemplary embodiments are described in relation with BCH encoding and decoding and LDPC encoding and decoding. However, these embodiments do not limit the inventive concept to only a particular encoding and decoding, and instead, the inventive concept may be applied to different types of encoding and decoding with necessary modifications. These modifications should also be understood to fall within the scope of the inventive concept. 

What is claimed is:
 1. A receiving method of a receiving apparatus which is operable in a mode among a plurality of modes, the receiving method: receive a signal from a transmitting apparatus; demodulating the signal to generate values; if the mode is a predetermined mode among the plurality of modes, adding first values of the generated values to second values of the generated values; and decoding the added values and remaining values of the generated values based on a low density parity check (LDPC) code, wherein the signal is generated by encoding information bits comprising input bits based on the LDPC code to generate parity bits, selecting one or more parity bits of the generated parity bits and appending the selected parity bits between the information bits and the generated parity bits, wherein a number of the parity bits to be selected is determined based on a following equation: N _(repeat)=2×└C×N _(outer) ┘+D, where N_(repeat) represents the number of the parity bits to be selected, N_(outer) represents a number of the input bits and C and D are predetermined values respectively, wherein the first values correspond to two or more parity bits among the appended parity bits, and wherein the second values correspond to two or more parity bits among the selected parity bits.
 2. The receiving method of claim 1, wherein the transmitting apparatus is configured to, if the number of the parity bits to be selected is equal to or less than a number of the generated parity bits, select bits from a first bit of the generated parity bits based on the number of the one or more parity bits to be selected, and append the selected parity bits to the information bits.
 3. The receiving method of claim 1, wherein, the transmitting apparatus is configured to, if the number of the one or more parity bits to be selected is greater than a number of the generated parity bits, select the generated parity bits, append the selected parity bits to the information bits, additionally select bits based on a number obtained by subtracting the number of the generated parity bits from the number of the parity bits to be selected, and append the additionally selected bits to the appended parity bits.
 4. A transmitting method of a transmitting apparatus which is operable based on a mode among a plurality of modes, the transmitting method comprising: encoding information bits comprising input bits to generate parity bits based on a low density parity check (LDPC) code, a code length of the LDPC code being 16200 bits; if the mode is a predetermined mode among the plurality of modes, performing a repetition by determining a number of repetition bits based on a number of the input bits, selecting one or more parity bits of the generated parity bits based on the determined number and a number of the generated parity bits and appending the selected bits between the information bits and the generated parity bits; puncturing one or more parity bits of the generated parity bits; if the mode is the predetermined mode, mapping the input bits, the appended parity bits and remaining parity bits of the generated parity bits after the puncturing to constellation points for a quadrature phase shift keying (QPSK); and transmitting a signal which is generated based on the constellation points.
 5. The transmitting method of claim 4, wherein if the determined number is equal to or less than the number of the generated parity bits, the one or more parity bits are selected from a first bit of the generated parity bits based on the determined number.
 6. The transmitting method of claim 4, wherein the selecting comprises if the determined number is greater than the number of the generated parity bits, the generated parity bits are selected, the selected parity bits are append to the information bits, at least one parity bit from a first bit of the generated parity bits based on a number obtained by subtracting the number of the generated parity bits from the determined number is selected, and the selected at least one parity bits is append to the appended parity bits. 